S25FL128SDPBFNA01 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL128SDPBFNA01
Cypress Semiconductor
S25FL128SDPBFNA01 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
Table 7.9 Configuration Register 1(CR1)
Bits
Field Name
Function
Type
Default
State
Description
7
LC1
6
LC0
Latency Code
Non-Volatile
0
Selects number of initial read latency cycles
0
See Latency Code Tables
5
TBPROT
Configures Start of Block
Protection
OTP
0
1 = BP starts at bottom (Low address)
0 = BP starts at top (High address)
4
RFU
RFU
OTP
0
Reserved for Future Use
3
BPNV
Configures BP2-0 in
Status Register
OTP
0
1 = Volatile
0 = Non-Volatile
2
TBPARM
Configures Parameter
Sectors location
OTP
1 = 4-kB physical sectors at top, (high address)
0
0 = 4-kB physical sectors at bottom (Low address)
RFU in uniform sector devices
1
QUAD
Puts the device into Quad
I/O operation
Non-Volatile
0
1 = Quad
0 = Dual or Serial
Lock current state of BP2-
0 bits in Status Register,
0
FREEZE
TBPROT and TBPARM in
Volatile
Configuration Register,
and OTP regions
0
1 = Block Protection and OTP locked
0 = Block Protection and OTP un-locked
Latency Code (LC) CR1[7:6]: The Latency Code selects the number of mode and dummy cycles between the end of address and
the start of read data output for all read commands.
Some read commands send mode bits following the address to indicate that the next command will be of the same type with an
implied, rather than an explicit, instruction. The next command thus does not provide an instruction byte, only a new address and
mode bits. This reduces the time needed to send each command when the same command type is repeated in a sequence of
commands.
Dummy cycles provide additional latency that is needed to complete the initial read access of the flash array before data can be
returned to the host system. Some read commands require additional latency cycles as the SCK frequency is increased.
The following latency code tables provide different latency settings that are configured by Cypress. The High Performance versus
the Enhanced High Performance settings are selected by the ordering part number.
Where mode or latency (dummy) cycles are shown in the tables as a dash, that read command is not supported at the frequency
shown. Read is supported only up to 50 MHz but the same latency value is assigned in each latency code and the command may be
used when the device is operated at 50 MHz with any latency code setting. Similarly, only the Fast Read command is supported
up to 133 MHz but the same 10b latency code is used for Fast Read up to 133 MHz and for the other dual and quad read commands
up to 104 MHz. It is not necessary to change the latency code from a higher to a lower frequency when operating at lower
frequencies where a particular command is supported. The latency code values for a higher frequency can be used for accesses at
lower frequencies.
The High Performance settings provide latency options that are the same or faster than alternate source SPI memories. These
settings provide mode bits only for the Quad I/O Read command.
The Enhanced High Performance settings similarly provide latency options the same or faster than additional alternate source SPI
memories and adds mode bits for the Dual I/O Read, DDR Fast Read, and DDR
Dual I/O Read commands.
Read DDR Data Learning Pattern (DLP) bits may be placed within the dummy cycles immediately before the start of read data, if
there are 5 or more dummy cycles. See Read Memory Array Commands on page 82 for more information on the DLP.
Document Number: 001-98283 Rev. *I
Page 50 of 144
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