S25FL128SDSMFN201 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL128SDSMFN201

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

9.3.5

Bank Register Write (BRWR 17h)

The Bank Register Write (BRWR) command is used to write address bits above A23, into the Bank Address Register (BAR). The

command is also used to write the Extended address control bit (EXTADD) that is also in BAR[7]. BAR provides the high order

addresses needed by devices having more than 128 Mbits (16 Mbytes), when using 3-byte address commands without extended

addressing enabled (BAR[7] EXTADD = 0). Because this command is part of the addressing method and is not changing data in the

flash memory, this command does not require the WREN command to precede it.

The BRWR instruction is entered, followed by the data byte on SI. The Bank Register is one data byte in length.

The BRWR command has no effect on the P_ERR, E_ERR or WIP bits of the Status and Configuration Registers. Any bank address

bit reserved for the future should always be written as a 0.

Figure 9.8 Bank Register Write (BRWR) Command

CS#

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

Bank Register In

7654321 0 7654321 0

MSB

MSB

High Impedance

9.3.6

Bank Register Access (BRAC B9h)

The Bank Register Read and Write commands provide full access to the Bank Address Register (BAR) but they are both commands

that are not present in legacy SPI memory devices. Host system SPI memory controller interfaces may not be able to easily support

such new commands. The Bank Register Access (BRAC) command uses the same command code and format as the Deep Power

Down (DPD) command that is available in legacy SPI memories. The FL-S family does not support a DPD feature but assigns this

legacy command code to the BRAC command to enable write access to the Bank Address Register for legacy systems that are able

to send the legacy DPD (B9h) command.

When the BRAC command is sent, the FL-S family device will then interpret an immediately following Write Register (WRR)

command as a write to the lower address bits of the BAR. A WREN command is not used between the BRAC and WRR commands.

Only the lower two bits of the first data byte following the WRR command code are used to load BAR[1:0]. The upper bits of that byte

and the content of the optional WRR command second data byte are ignored. Following the WRR command the access to BAR is

closed and the device interface returns to the standby state. The combined BRAC followed by WRR command sequence has no

affect on the value of the ExtAdd bit (BAR[7]).

Commands other than WRR may immediately follow BRAC and execute normally. However, any command other than WRR, or any

other sequence in which CS# goes low and returns high, following a BRAC command, will close the access to BAR and return to the

normal interpretation of a WRR command as a write to Status Register-1 and the Configuration Register.

The BRAC + WRR sequence is allowed only when the device is in standby, program suspend, or erase suspend states. This

command sequence is illegal when the device is performing an embedded algorithm or when the program (P_ERR) or erase

(E_ERR) status bits are set to 1.

Document Number: 001-98283 Rev. *I

Page 74 of 144

Share Link: