S25FL256SDPBFVB10 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDPBFVB10

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

Figure 9.9 BRAC (B9h) Command Sequence

CS#

SCK

SI

SO

0 12 3 4 5 6 7

Instruction

76543210

MSB

High Impedance

9.3.7

Write Registers (WRR 01h)

The Write Registers (WRR) command allows new values to be written to both the Status Register-1 and Configuration Register.

Before the Write Registers (WRR) command can be accepted by the device, a Write Enable (WREN) command must be received.

After the Write Enable (WREN) command has been decoded successfully, the device will set the Write Enable Latch (WEL) in the

Status Register to enable any write operations.

The Write Registers (WRR) command is entered by shifting the instruction and the data bytes on SI. The Status Register is one data

byte in length.

The Write Registers (WRR) command will set the P_ERR or E_ERR bits if there is a failure in the WRR operation. Any Status or

Configuration Register bit reserved for the future must be written as a 0.

CS# must be driven to the logic high state after the eighth or sixteenth bit of data has been latched. If not, the Write Registers (WRR)

command is not executed. If CS# is driven high after the eighth cycle then only the Status Register-1 is written; otherwise, after the

sixteenth cycle both the Status and Configuration Registers are written. When the configuration register QUAD bit CR[1] is 1, only

the WRR command format with 16 data bits may be used.

As soon as CS# is driven to the logic high state, the self-timed Write Registers (WRR) operation is initiated. While the Write

Registers (WRR) operation is in progress, the Status Register may still be read to check the value of the Write-In Progress (WIP) bit.

The Write-In Progress (WIP) bit is a 1 during the self-timed Write Registers (WRR) operation, and is a 0 when it is completed. When

the Write Registers (WRR) operation is completed, the Write Enable Latch (WEL) is set to a 0. The maximum clock frequency for the

WRR command is 133 MHz.

Figure 9.10 Write Registers (WRR) Command Sequence – 8 data bits

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SCK

Instruction

Status Register In

SI

7654321 0

MSB

High Impedance

SO

Document Number: 001-98283 Rev. *I

Page 75 of 144

Share Link: