S25FL256SAGNFN701 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL256SAGNFN701
Cypress Semiconductor
S25FL256SAGNFN701 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
Figure 9.11 Write Registers (WRR) Command Sequence – 16 data bits
CS#
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
High Impedance
Status Register In
Configuration Register In
7654321 07654321 0
MSB
MSB
The Write Registers (WRR) command allows the user to change the values of the Block Protect (BP2, BP1, and BP0) bits to define
the size of the area that is to be treated as read-only. The Write Registers (WRR) command also allows the user to set the Status
Register Write Disable (SRWD) bit to a 1 or a 0. The Status Register Write Disable (SRWD) bit and Write Protect (WP#) signal allow
the BP bits to be hardware protected.
When the Status Register Write Disable (SRWD) bit of the Status Register is a 0 (its initial delivery state), it is possible to write to the
Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) command,
regardless of the whether Write Protect (WP#) signal is driven to the logic high or logic low state.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to a 1, two cases need to be considered, depending
on the state of Write Protect (WP#):
If Write Protect (WP#) signal is driven to the logic high state, it is possible to write to the Status and Configuration Registers
provided that the Write Enable Latch (WEL) bit has previously been set to a 1 by initiating a Write Enable (WREN)
command.
If Write Protect (WP#) signal is driven to the logic low state, it is not possible to write to the Status and Configuration
Registers even if the Write Enable Latch (WEL) bit has previously been set to a 1 by a Write Enable (WREN) command.
Attempts to write to the Status and Configuration Registers are rejected, and are not accepted for execution. As a
consequence, all the data bytes in the memory area that are protected by the Block Protect (BP2, BP1, BP0) bits of the
Status Register, are also hardware protected by WP#.
The WP# hardware protection can be provided:
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (WP#) signal to the logic low state;
or by driving Write Protect (WP#) signal to the logic low state after setting the Status Register Write Disable (SRWD) bit to a 1.
The only way to release the hardware protection is to pull the Write Protect (WP#) signal to the logic high state. If WP# is
permanently tied high, hardware protection of the BP bits can never be activated.
Table 9.5 Block Protection Modes
WP#
1
1
0
0
SRWD Bit
1
0
0
1
Mode
Write Protection of Registers
Software Protected
Status and Configuration Registers are Writable (if WREN
command has set the WEL bit). The values in the SRWD,
BP2, BP1, and BP0 bits and those in the Configuration
Register can be changed
Hardware
Protected
Status and Configuration Registers are Hardware Write
Protected. The values in the SRWD, BP2, BP1, and BP0 bits
and those in the Configuration Register cannot be changed
Memory Content
Protected Area
Unprotected Area
Protected against Page
Program, Quad Input
Program, Sector Erase,
and Bulk Erase
Ready to accept Page
Program, Quad Input
Program and Sector
Erase commands
Protected against Page
Program, Sector Erase,
and Bulk Erase
Ready to accept Page
Program or Erase
commands
Notes:
1. The Status Register originally shows 00h when the device is first shipped from Cypress to the customer.
2. Hardware protection is disabled when Quad Mode is enabled (QUAD bit = 1 in Configuration Register). WP# becomes IO2; therefore, it cannot be utilized.
The WRR command has an alternate function of loading the Bank Address Register if the command immediately follows a BRAC
command. See Bank Register Access (BRAC B9h) on page 74.
Document Number: 001-98283 Rev. *I
Page 76 of 144
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