S25FL256SDPNFVD01 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDPNFVD01

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

9.3.12

AutoBoot Register Read (ABRD 14h)

The AutoBoot Register Read command is shifted into SI. Then the 32-bit AutoBoot Register is shifted out on SO, least significant

byte first, most significant bit of each byte first. It is possible to read the AutoBoot Register continuously by providing multiples of 32

clock cycles. If the QUAD bit CR1[1] is cleared to 0, the maximum operating clock frequency for ABRD command is 133 MHz. If the

QUAD bit CR1[1] is set to 1, the maximum operating clock frequency for ABRD command is 104 MHz.

Figure 9.17 AutoBoot Register Read (ABRD) Command

CS#

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 11

37 38 39 40

Instruction

76

MSB

54321

High Impedance

0

76

MSB

AutoBoot Register

54

26 25 24 7

MSB

9.3.13

AutoBoot Register Write (ABWR 15h)

Before the ABWR command can be accepted, a Write Enable (WREN) command must be issued and decoded by the device, which

sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The ABWR command is entered by shifting the instruction and the data bytes on SI, least significant byte first, most significant bit of

each byte first. The ABWR data is 32 bits in length.

The ABWR command has status reported in Status Register-1 as both an erase and a programming operation. An E_ERR or a

P_ERR may be set depending on whether the erase or programming phase of updating the register fails.

CS# must be driven to the logic high state after the 32nd bit of data has been latched. If not, the ABWR command is not executed.

As soon as CS# is driven to the logic high state, the self-timed ABWR operation is initiated. While the ABWR operation is in

progress, Status Register-1 may be read to check the value of the Write-In Progress (WIP) bit. The Write-In Progress (WIP) bit is a

1 during the self-timed ABWR operation, and is a 0. when it is completed. When the ABWR cycle is completed, the Write Enable

Latch (WEL) is set to a 0. The maximum clock frequency for the ABWR command is 133 MHz.

Figure 9.18 AutoBoot Register Write (ABWR) Command

CS#

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10

36 37 38 39

Instruction

AutoBoot Register

7654321 0 765

MSB

High Impedance

MSB

27 26 25 24

Document Number: 001-98283 Rev. *I

Page 80 of 144

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