S25FL128SDPMHVB11 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL128SDPMHVB11

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

9.3.14

Program NVDLR (PNVDLR 43h)

Before the Program NVDLR (PNVDLR) command can be accepted by the device, a Write Enable (WREN) command must be

issued and decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the

Write Enable Latch (WEL) to enable the PNVDLR operation.

The PNVDLR command is entered by shifting the instruction and the data byte on SI.

CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the PNVDLR command is not

executed. As soon as CS# is driven to the logic high state, the self-timed PNVDLR operation is initiated. While the PNVDLR

operation is in progress, the Status Register may be read to check the value of the Write-In Progress (WIP) bit. The Write-In

Progress (WIP) bit is a 1 during the self-timed PNVDLR cycle, and is a 0. when it is completed. The PNVDLR operation can report a

program error in the P_ERR bit of the status register. When the PNVDLR operation is completed, the Write Enable Latch (WEL) is

set to a 0 The maximum clock frequency for the PNVDLR command is 133 MHz.

Figure 9.19 Program NVDLR (PNVDLR) Command Sequence

CS#

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

SCK

Instruction

Data Learning Pattern

SI

76543 2 1 0 765 43 2 1 0

MSB

MSB

High Im pedance

SO

9.3.15

Write VDLR (WVDLR 4Ah)

Before the Write VDLR (WVDLR) command can be accepted by the device, a Write Enable (WREN) command must be issued and

decoded by the device. After the Write Enable (WREN) command has been decoded successfully, the device will set the Write

Enable Latch (WEL) to enable WVDLR operation.

The WVDLR command is entered by shifting the instruction and the data byte on SI.

CS# must be driven to the logic high state after the eighth (8th) bit of data has been latched. If not, the WVDLR command is not

executed. As soon as CS# is driven to the logic high state, the WVDLR operation is initiated with no delays. The maximum clock

frequency for the PNVDLR command is 133 MHz.

Figure 9.20 Write VDLR (WVDLR) Command Sequence

CS#

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

Data Learning Pattern

76543 2 1 0 765 43 2 1 0

MSB

High Impedance

MSB

Document Number: 001-98283 Rev. *I

Page 81 of 144

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