S25FL128SDPMFNG13 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL128SDPMFNG13

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

Figure 9.31 Quad Output Read Command Sequence (4-byte Address, 6Ch or 6Bh [ExtAdd=1, LC=01b])

CS#

SCK

IO0

012345678

38 39 40 41 42 43 44 45 46 47 48 49 50 51

Instruction

32 Bit Address

7 6 5 4 3 2 1 0 31

10

8 Dummy Cycles

Data 1

40

Data 2

40

IO1

5151

IO2

6262

IO3

7373

Figure 9.32 Quad Output Read Command Sequence (4-byte Address, 6Ch or 6Bh [ExtAdd=1], LC=11b)

CS#

SCK

IO0

IO1

IO2

IO3

012345678

38 39 40 41 42 43 44 45 46 47

Instruction

32 Bit Address

Data 1 Data 2 Data 3 Data 3

7 6 5 4 3 2 1 0 31

1040404040

5 1515151

6 2626262

7 3737373

9.4.5

Dual I/O Read (DIOR BBh or 4DIOR BCh)

The instruction

BBh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

BBh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

BCh is followed by a 4-byte address (A31-A0)

The Dual I/O Read commands improve throughput with two I/O signals — IO0 (SI) and IO1 (SO). It is similar to the Dual Output

Read command but takes input of the address two bits per SCK rising edge. In some applications, the reduced address input time

might allow for code execution in place (XIP) i.e. directly from the memory device.

The maximum operating clock frequency for Dual I/O Read is 104 MHz.

For the Dual I/O Read command, there is a latency required after the last address bits are shifted into SI and SO before data begins

shifting out of IO0 and IO1. There are different ordering part numbers that select the latency code table used for this command,

either the High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC) table. The HPLC table does not

provide cycles for mode bits so each Dual I/O Read command starts with the 8 bit instruction, followed by address, followed by a

latency period.

This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial address. During the

dummy cycles, the data value on SI and SO are “don’t care” and may be high impedance. The number of dummy cycles is

determined by the frequency of SCK (Table 7.12, Latency Codes for SDR Enhanced High Performance on page 51). The number of

dummy cycles is set by the LC bits in the Configuration Register (CR1).

The EHPLC table does provide cycles for mode bits so a series of Dual I/O Read commands may eliminate the 8-bit instruction after

the first Dual I/O Read command sends a mode bit pattern of Axh that indicates the following command will also be a Dual I/O Read

command. The first Dual I/O Read command in a series starts with the 8-bit instruction, followed by address, followed by four cycles

of mode bits, followed by a latency period. If the mode bit pattern is Axh the next command is assumed to be an additional Dual I/O

Document Number: 001-98283 Rev. *I

Page 87 of 144

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