S25FL256SDPMFNB03 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL256SDPMFNB03
Cypress Semiconductor
S25FL256SDPMFNB03 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
Address jumps can be done without the need for additional Quad I/O Read instructions. This is controlled through the setting of the
Mode bits (after the address sequence, as shown in Figure 9.37 on page 90 or Figure 9.39 on page 91). This added feature
removes the need for the instruction sequence and greatly improves code execution (XIP). The upper nibble (bits 7-4) of the Mode
bits control the length of the next Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower
nibble (bits 3-0) of the Mode bits are “don’t care” (“x”). If the Mode bits equal Axh, then the device remains in Quad I/O High
Performance Read Mode and the next address can be entered (after CS# is raised high and then asserted low) without requiring the
EBh or ECh instruction, as shown in Figure 9.38 on page 90 or Figure 9.40 on page 91; thus, eliminating eight cycles for the
command sequence. The following sequence will release the device from Quad I/O High Performance Read mode; after which, the
device can accept standard SPI commands:
During the Quad I/O Read Command Sequence, if the Mode bits are any value other than Axh, then the next time CS# is
raised high the device will be released from Quad I/O High Performance Read mode.
During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0-IO3) are not set for a valid
instruction sequence, then the device will be released from Quad I/O High Performance Read mode. Note that the two mode bit
clock cycles and additional wait states (i.e., dummy cycles) allow the device’s internal circuitry latency time to access the initial
address after the last address cycle that is clocked into IO0-IO3.
It is important that the IO0-IO3 signals be set to high-impedance at or before the falling edge of the first data out clock. At higher
clock speeds the time available to turn off the host outputs before the memory device begins to drive (bus turn around) is diminished.
It is allowed and may be helpful in preventing IO0-IO3 signal contention, for the host system to turn off the IO0-IO3 signal outputs
(make them high impedance) during the last “don’t care” mode cycle or during any dummy cycles.
CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate.
CS#
SCK
IO0
IO1
IO2
IO3
Figure 9.37 Quad I/O Read Command Sequence (3-byte Address, EBh [ExtAdd=0], LC=00b)
012345678
12 13 14 15 16 17 18 19 20 21 22 23
8 cycles
Instruction
6 cycles
24 Bit Address
2 cycles
Mode
7 6 5 4 3 2 1 0 20
4
0
40
1
21
51 5
22
6
2
62
23
7
3
73
4 cycles
Dummy
2 cycles
Data 1
40
Data 2
40
5151
6261
7371
Figure 9.38 Continuous Quad I/O Read Command Sequence (3-byte Address), LC=00b
CS#
SCK
IO0
2 cycles
Data N
40
2 cycles
Data N+1
40
IO1 5 1 5 1
IO2 6 2 6 2
IO3 7 3 7 3
0
4 5 6 7 8 9 10 11 12 13 14
6 cycles
24 Bit Address
20
40
21
51
22
62
23
73
2 cycles
Mode
4
0
5
1
6
2
3
7
4 cycles
Dummy
2 cycles
Data 1
40
51
62
73
2 cycles
Data 2
40
51
61
71
Document Number: 001-98283 Rev. *I
Page 90 of 144
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