S25FL128SAGNFIF01 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL128SAGNFIF01
Cypress Semiconductor
S25FL128SAGNFIF01 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
Figure 9.39 Quad I/O Read Command Sequence(4-byte Address, ECh or EBh [ExtAdd=1], LC=00b)
CS#
012345678
14 15 16 17 18 19 20 21 22 23 24 25
SCK
8 cycles
Instruction
8 cycles
32 Bit Address
2 cycles
Mode
IO0 7 6 5 4 3 2 1 0 28
0
40 4
1
IO1
29
51 5
2
IO2
30
62 6
IO3
31
7
3
73
4 cycles
Dummy
2 cycles
Data 1
40
Data 2
40
5151
6261
7371
Figure 9.40 Continuous Quad I/O Read Command Sequence (4-byte Address), LC=00b
CS#
SCK
IO0
2 cycles
Data N
40
2 cycles
Data N+1
40
IO1 5 1 5 1
IO2 6 2 6 2
IO3 7 3 7 3
0
6 7 8 9 10 11 12 13 14 15 16
8 cycles
32 Bit Address
28
40
29
51
30
62
31
73
2 cycles
Mode
0
4
1
5
2
6
7
3
4 cycles
Dummy
2 cycles
Data 1
40
51
62
73
2 cycles
Data 2
40
51
61
71
9.4.7
DDR Fast Read (DDRFR 0Dh, 4DDRFR 0Eh)
The instruction
0Dh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or
0Dh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or
0Eh is followed by a 4-byte address (A31-A0)
The DDR Fast Read command improves throughput by transferring address and data on both the falling and rising edge of SCK. It
is similar to the Fast Read command but allows transfer of address and data on every edge of the clock.
The maximum operating clock frequency for DDR Fast Read command is 80 MHz.
For the DDR Fast Read command, there is a latency required after the last address bits are shifted into SI before data begins
shifting out of SO. There are different ordering part numbers that select the latency code table used for this command, either the
High Performance LC (HPLC) table or the Enhanced High Performance LC (EHPLC) table. The HPLC table does not provide cycles
for mode bits so each DDR Fast Read command starts with the 8 bit instruction, followed by address, followed by a latency period.
This latency period (dummy cycles) allows the device internal circuitry enough time to access data at the initial address. During the
dummy cycles, the data value on SI is “don’t care” and may be high impedance. The number of dummy cycles is determined by the
frequency of SCK (Table 7.12, Latency Codes for SDR Enhanced High Performance on page 51). The number of dummy cycles is
set by the LC bits in the Configuration Register (CR1).
Document Number: 001-98283 Rev. *I
Page 91 of 144
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