S25FL128SDPBFID03 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
Manufacturer
S25FL128SDPBFID03
Cypress Semiconductor
S25FL128SDPBFID03 Datasheet PDF : 144 Pages
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S25FL128S, S25FL256S
The preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to
when the corresponding data value returns from the memory device. The host controller will skew the data capture point during the
preamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read
operation. The optimized capture point will be determined during the preamble period of every read operation. This optimization
strategy is intended to compensate for both the PVT (process, voltage, temperature) of both the memory device and the host
controller as well as any system level delays caused by flight time on the PCB.
Although the data learning pattern (DLP) is programmable, the following example shows example of the DLP of 34h. The DLP 34h
(or 00110100) will be driven on each of the active outputs (i.e. all four SIOs on a x4 device, both SIOs on a x2 device and the single
SO output on a x1 device). This pattern was chosen to cover both DC and AC data transition scenarios. The two DC transition
scenarios include data low for a long period of time (two half clocks) followed by a high going transition (001) and the complementary
low going transition (110). The two AC transition scenarios include data low for a short period of time (one half clock) followed by a
high going transition (101) and the complementary low going transition (010). The DC transitions will typically occur with a starting
point closer to the supply rail than the AC transitions that may not have fully settled to their steady state (DC) levels. In many cases
the DC transitions will bound the beginning of the data valid period and the AC transitions will bound the ending of the data valid
period. These transitions will allow the host controller to identify the beginning and ending of the valid data eye. Once the data eye
has been characterized the optimal data capture point can be chosen. See Section 7.5.11, SPI DDR Data Learning Registers
on page 55 for more details.
Figure 9.46 DDR Dual I/O Read Initial Access (4-byte Address, BEh or BDh [ExtAdd=1], EHPLC= 01b)
CS#
0
1
2
3
4
5
6
7
8
15
16
17
18
19
20
21
22
23
24
25
SCK
8 cycles
Instruction
8 cycles
32b Add
2 cycles
Mode
5 cycles Dummy
Optional DLP
2 cycles
per data
IO0
7
6
5
4
3
2
1
0
30 22 2 0 6 4 2 0
7 654321064206
IO1
31 22 3 1 7 5 3 1
7 654321075317
Figure 9.47 Continuous DDR Dual I/O Read Subsequent Access (4-byte Address, EHPLC= 01b)
CS#
0
8
9
10
11
12
13
14
8
15
16
17
SCK
8 cycles
32b Add
2 cycles
Mode
5 cycles Dummy
Optional DLP
2 cycles
per data
IO0
30 22 2
0
6
4
2
0
7
6
5
4
3
2
1
0
6
4
2
0
6
IO1
31 22 3
1
7
5
3
1
7
6
5
4
3
2
1
0
7
5
3
1
7
Figure 9.48 DDR Dual I/O Read (4-byte Address, BEh or BDh [ExtAdd=1], HPLC=00b)
CS#
0
1
2
3
4
5
6
7
8
15
16
17
18
19
20
21
22
23
24
SCK
8 cycles
Instruction
8 cycles
32b Add
6 cycles
Dummy
2 cycles
per data
IO0
7
6
5
4
3
2
1
0
30
20
6 4206
IO1
31
31
7 53172
Document Number: 001-98283 Rev. *I
Page 95 of 144
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