S25FL256SDPNHNG11 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

Manufacturer

S25FL256SDPNHNG11

128 Mbit (16 Mbyte), 256 Mbit (32 Mbyte) 3.0V SPI Flash Memory

Cypress Semiconductor 

S25FL128S, S25FL256S

9.4.9

DDR Quad I/O Read (EDh, EEh)

The Read DDR Quad I/O command improves throughput with four I/O signals - IO0-IO3. It is similar to the Quad I/O Read command

but allows input of the address four bits on every edge of the clock. In some applications, the reduced instruction overhead might

allow for code execution (XIP) directly from S25FL128S and S25FL256S devices. The QUAD bit of the Configuration Register must

be set (CR Bit1=1) to enable the Quad capability.

The instruction

EDh (ExtAdd=0) is followed by a 3-byte address (A23-A0) or

EDh (ExtAdd=1) is followed by a 4-byte address (A31-A0) or

EEh is followed by a 4-byte address (A31-A0)

The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a DDR fashion, with four

bits at a time on each clock edge through IO0-IO3.

The maximum operating clock frequency for Read DDR Quad I/O command is 80 MHz.

For Read DDR Quad I/O, there is a latency required after the last address and mode bits are shifted into the IO0-IO3 signals before

data begins shifting out of IO0-IO3. This latency period (dummy cycles) allows the device’s internal circuitry enough time to access

the initial address. During these latency cycles, the data value on IO0-IO3 are “don’t care” and may be high impedance. When the

Data Learning Pattern (DLP) is enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must

be left high impedance by the host so that the memory device can drive the DLP during the dummy cycles.

There are different ordering part numbers that select the latency code table used for this command, either the High Performance LC

(HPLC) table or the Enhanced High Performance LC (EHPLC) table. The number of dummy cycles is determined by the frequency

of SCK (refer to Table 7.11, Latency Codes for DDR High Performance on page 51). The number of dummy cycles is set by the LC

bits in the Configuration Register (CR1).

Both latency tables provide cycles for mode bits so a series of Quad I/O DDR commands may eliminate the 8 bit instruction after the

first command sends a complementary mode bit pattern, as shown in Figure 9.49 and Figure 9.51. This feature removes the need

for the eight bit SDR instruction sequence and dramatically reduces initial access times (improves XIP performance). The Mode bits

control the length of the next Read DDR Quad I/O operation through the inclusion or exclusion of the first byte instruction code. If the

upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits are complementary (i.e. 5h and Ah) the device transitions to

Continuous Read DDR Quad I/O Mode and the next address can be entered (after CS# is raised high and then asserted low)

without requiring the EDh or EEh instruction, as shown in Figure 9.50 on page 97 and Figure 9.52 on page 98 thus, eliminating eight

cycles from the command sequence. The following sequences will release the device from Continuous Read DDR Quad I/O mode;

after which, the device can accept standard SPI commands:

1. During the Read DDR Quad I/O Command Sequence, if the Mode bits are not complementary the next time CS# is raised

high and then asserted low the device will be released from Read DDR Quad I/O mode.

2. During any operation, if CS# toggles high to low to high for eight cycles (or less) and data input (IO0, IO1, IO2, and IO3)

are not set for a valid instruction sequence, then the device will be released from Read DDR Quad I/O mode.

The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address

in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read

instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back

to 000000h, allowing the read sequence to be continued indefinitely.

CS# should not be driven high during mode or dummy bits as this may make the mode bits indeterminate. The HOLD function is not

valid during Quad I/O DDR commands.

Note that the memory devices drive the IOs with a preamble prior to the first data value. The preamble is a pattern that is used by the

host controller to optimize data capture at higher frequencies. The preamble drives the IO bus for the four clock cycles immediately

before data is output. The host must be sure to stop driving the IO bus prior to the time that the memory starts outputting the

preamble.

The preamble is intended to give the host controller an indication about the round trip time from when the host drives a clock edge to

when the corresponding data value returns from the memory device. The host controller will skew the data capture point during the

preamble period to optimize timing margins and then use the same skew time to capture the data during the rest of the read

operation. The optimized capture point will be determined during the preamble period of every read operation. This optimization

strategy is intended to compensate for both the PVT (process, voltage, temperature) of both the memory device and the host

controller as well as any system level delays caused by flight time on the PCB.

Document Number: 001-98283 Rev. *I

Page 96 of 144

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