AM28F512-70FIB View Datasheet(PDF) - Advanced Micro Devices

Part Name

Description

Manufacturer

AM28F512-70FIB

512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory

Advanced Micro Devices 

Section

Addresses

A

B

C

D

E

F

G

CE#

OE#

WE#

Data

VCC

20h

Data

In

A0h

Data

Out

VPP

Bus Cycle

Command

Function

A

Write

40h

Program

Setup

B

Write

Program

Address,

Program Data

Program

Command

Latch

Address and

Data

C

Time-out

N/A

Program

(10 µs)

D

Write

C0h

(Stops

Program)

Program

Verify

E

Time-out

N/A

F

Read

Compare

Data

11559G-9

G

Standby

N/A

Transition

(6 µs)

Program

Verification

Proceed per

Programming

Algorithm

Figure 4. AC Waveforms for Programming Operations

ANALYSIS OF PROGRAM TIMING

WAVEFORMS

Program Setup/Program

Two-cycle write commands are required for program

operations (section A and B). The first program com-

mand (40h) is a Setup command and does not affect

the array data (section A).The second program com-

mand latches address and data required for program-

ming on the falling and rising edge of WE# respectively

(section B). The rising edge of this WE# pulse (section

B) also initiates the programming pulse. The device is

programmed on a byte by byte basis either sequentially

or randomly.

The program pulse occurs in section C.

Time-Out

A software timing routine (10 µs duration) must be initi-

ated on the rising edge of the WE# pulse of section B.

Note: An integrated stop timer prevents any possibility

of overprogramming by limiting each time-out period of

10 µs.

Program-Verify

Upon completion of the program timing routine, the mi-

croprocessor must write the program-verify command

(C0h). This command terminates the programming op-

eration on the rising edge of the WE# pulse (section D).

The program-verify command also stages the device

for data verification (section F). Another software timing

routine (6 µs duration) must be executed to allow for

18

Am28F512

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