M38861M2AFS View Datasheet(PDF) - Renesas Electronics
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Description
Manufacturer
M38861M2AFS Datasheet PDF : 111 Pages
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MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MULTI-MASTER I2C-BUS INTERFACE
The multi-master I2C-BUS interface is a serial communications cir-
cuit, conforming to the Philips I2C-BUS data transfer format. This
interface, offering both arbitration lost detection and a synchro-
nous functions, is useful for the multi-master serial
communications.
Figure 35 shows a block diagram of the multi-master I2C-BUS in-
terface and Table 9 lists the multi-master I2C-BUS interface
functions.
This multi-master I2C-BUS interface consists of the I2C address
register, the I2C data shift register, the I2C clock control register,
the I2C control register, the I2C status register, the I2C start/stop
condition control register and other control circuits.
When using the multi-master I2C-BUS interface, set 1 MHz or
more to φ.
Table 9 Multi-master I2C-BUS interface functions
Item
Format
Communication mode
SCL clock frequency
Function
In conformity with Philips I2C-BUS
standard:
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
In conformity with Philips I2C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
16.1 kHz to 400 kHz (at φ= 4 MHz)
20.2 kHz to 312.5 kHz (at φ = 5 MHz)
System clock φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
Interrupt
generating
circuit
b7
I2C address register
b0
Interrupt request signal SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
(SCLSDAIRQ)
S0D
Interrupt
generating
circuit
Interrupt request signal
(I2CIRQ)
Serial data
(SDA)
Noise
elimination
circuit
S2D
STSP
SEL
SIS
SIP SSC4 SSC3 SSC2 SSC1 SSC0
I2C start/stop condition
control register
Data
control
b7
circuit
S0
AL
circuit
Address comparator
I2C data shift register
b0
b7
b0
AL AAS AD0 LRB
MST TRX BB PIN
S1
I2C status register
Internal data bus
BB
circuit
Serial
clock
(SCL)
Noise
elimination
circuit
Clock
control
circuit
b7
b0
ACK
ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0
BIT MODE
S2
I2C clock control register
Clock division
Stop selection
I2C clock control register
b7
S1D b0
CLK 10BIT
TISS STP SAD ALS ES0 BC2 BC1 BC0
System clock (φ)
Bit counter
Fig. 35 Block diagram of multi-master I2C-BUS interface
V : Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components
an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
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