S25FL032P0XMHA021 View Datasheet(PDF) - Cypress Semiconductor
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S25FL032P0XMHA021 Datasheet PDF : 60 Pages
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S25FL032P
Block Protect (BP2, BP1, BP0) bits: Define the portion of the memory area that will be protected against any changes to the stored
data. The Block Protection (BP2, BP1, BP0) bits are either volatile or non-volatile, depending on the state of the nonvolatile bit BPNV
in the Configuration register. The Block Protection (BP2, BP1, BP0) bits are written with the Write Registers (WRR) instruction.
When one or more of the Block Protect (BP2, BP1, BP0) bits is set to 1’s, the relevant memory area is protected against Page
Program (PP), Parameter Sector Erase (P4E, P8E), Sector Erase (SE), Quad Page Programming (QPP) and Bulk Erase (BE)
instructions. If the Hardware Protected mode is enabled, BP2:BP0 cannot be changed.
The Bulk Erase (BE) instruction can be executed only when the Block Protection (BP2, BP1, BP0) bits are set to 0s. The default
condition of the BP2-0 bits is binary 000 (all 0s).
Erase Error bit (E_ERR): The Erase Error Bit is used as a Erase operation success and failure check. When the Erase Error bit is
set to a “1”, it indicates that there was an error which occurred in the last erase operation. With the Erase Error bit set to a “1”, this bit
is reset with the Clear Status Register (CLSR) command.
Program Error bit (P_ERR): The Program Error Bit is used as a Program operation success and failure check. When the Program
Error bit is set to a “1”, it indicates that there was an error which occurred in the last program operation. With the Program Error bit
set to a “1”, this bit is reset with the Clear Status Register (CLSR) command.
n Status Register Write Disable (SRWD) bit: Provides data protection when used together with the Write Protect (W#/ACC) signal.
ig The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W#/ACC) input pin. The Status
s Register Write Disable (SRWD) bit and the Write Protect (W#/ACC) signal allow the device to be put in the Hardware Protected
De mode. With the Status Register Write Disable (SRWD) bit set to a “1” and the W#/ACC driven to the logic low state, the device enters
the Hardware Protected mode; the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) and the nonvolatile bits of the
w Configuration Register (TBPARM, TBPROT, BPNV and QUAD) become read-only bits and the Write Registers (WRR) instruction
e opcode is no longer accepted for execution.
N Note: The P_ERR and E_ERR bits will not be set to a 1 if the application writes to a protected memory area.
for 9.12 Read Configuration Register (RCR)
d The Read Configuration Register (RCR) instruction opcode allows the Configuration Register contents to be read out of the SO
e serial output pin. The Configuration Register contents may be read at any time, even while a program, erase, or write cycle is in
d progress. When one of these cycles is in progress, it is recommended to the user to check the Write In Progress (WIP) bit of the
n Status Register before issuing a new instruction opcode to the device. The Configuration Register originally shows 00h when the
e device is first shipped from the factory to the customer. Refer to Section 7.8 on page 12 for more details.
m Figure 23. Read Configuration Register (RCR) Instruction Sequence
com CS#
Not Re SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
SI
Configuration Register Out
Configuration Register Out
High Impedance
SO
7 6 5 4 3 2 1 07 6 5 4 3 2 1 0 7
MSB
MSB
MSB
Document Number: 002-00650 Rev. *L
Page 31 of 60
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