PIC16F785/HV785
4.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT
Figure 4-5 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
• General purpose I/O
• Analog input for the A/D
• TMR1 gate input
• Crystal/resonator connection
• Clock output
FIGURE 4-5:
Data Bus
DQ
WR
WPUA
CK Q
RD
WPUA
BLOCK DIAGRAM OF RA4
ANS3
CLK(1)
Modes
VDD
Weak
RAPU
Oscillator
Circuit
OSC1
VDD
WR
PORTA
DQ
CK Q
WR
TRISA
D SQ
CK Q
RD
TRISA
RD
PORTA
DQ
WR
IOCA
CK Q
RD
IOCA
FOSC/4 1
0
CLKOUT
Enable
INTOSC/
RC/EC(2)
I/O pin
VSS
CLKOUT
Enable
ANS3
QD
EN
QD
EN Q1
Interrupt-on-
CHANGE
QD
Q3
EN
RD PORTA
To T1G
To A/D Converter
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
4.2.3.6 RA5/T1CKI/OSC1/CLKIN
Figure 4-6 shows the diagram for this pin. The RA5 pin
is configurable to function as one of the following:
• General purpose I/O
• TMR1 clock input
• Crystal/resonator connection
• Clock input
FIGURE 4-6:
BLOCK DIAGRAM OF RA5
Data Bus
DQ
WR
WPUA
CK Q
RD
WPUA
WR
PORTA
DQ
CK Q
INTOSC
Mode
CLK modes(1)
VDD
Weak
RAPU
Oscillator
VDD
Circuit
OSC2
I/O pin
WR
TRISA
D SQ
CK Q
RD
TRISA
RD
PORTA
DQ
WR
IOCA
CK Q
RD
IOCA
VSS
INTOSC
Mode
(2)
QD
EN
QD
EN Q1
Interrupt-on-
Change
QD
Q3
EN
RD PORTA
To TMR1 or CLKGEN
Note
1: CLK modes are XT, HS, LP and LPTMR1.
2: When using Timer1 with LP oscillator, the
Schmitt Trigger is bypassed.
DS41249E-page 40
© 2008 Microchip Technology Inc.