M48Z2M1PL View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
M48Z2M1PL Datasheet PDF : 12 Pages
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M48Z2M1, M48Z2M1Y
Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
A0-A20
E
G
DQ0-DQ7
tAVAV
VALID
tAVQV
tELQV
tELQX
tGLQV
tGLQX
tAXQX
tEHQZ
tGHQZ
DATA OUT
AI02052
Note: Write Enable (W) = High.
DATA RETENTION MODE
With valid VCC applied, the M48Z2M1/2M1Y oper-
ates as a conventional BYTEWIDEâ„¢ static RAM.
Should the supply voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself tWP after VCC falls below VPFD. All outputs
become high impedance, and all inputs are treated
as "don’t care."
If power fail detection occurs during a valid access,
the memory cycle continues to completion. If the
memory cycle fails to terminate within the time tWP,
write protection takes place. When VCC drops be-
low VSO, the control circuit switches power to the
internal energy source which preserves data.
The internal coin cells will maintain data in the
M48Z2M1/2M1Y after the initial application of VCC
for an accumulated period of at least 10 years when
VCC is less than VSO. As system power returns and
VCC rises above VSO, the batteries are discon-
nected, and the power supply is switched to exter-
nal Vcc. Write protection continues for tER after VCC
reaches VPFD to allow for processor stabilization.
After tER, normal RAM operation can resume.
For more information on Battery Storage life refer
to the Application Note AN1012.
7/12
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