ST6253C ST6263C ST6263B ST6260C ST6260B
CLOCK SYSTEM (Cont’d)
Figure 12. Clock Circuit Block Diagram
MAIN
OSCILLATOR
OSG
POR
: 13
Core
TIMER 1
M
U
fINT
OSCILLATOR
DIVIDER
: 12
Watchdog
X
RS0,RS1
LFAO
:1
Main Oscillator off
Figure 13. Maximum Operating Frequency (fMAX) versus Supply Voltage (VDD)
Maximum FREQUENCY (MHz)
8
7
4
6
5
4
3
fOSG
fOSG Min (at 85°C)
2
3
fOSG Min (at 125°C)
2
1
1
2.5
3
3.6
4
4.5
5
5.5
6
SUPPLY VOLTAGE (VDD)
VR01807J
Notes:
1. In this area, operation is guaranteed at the
quartz crystal frequency.
2. When the OSG is disabled, operation in this
area is guaranteed at the crystal frequency. When
the OSG is enabled, operation in this area is guar-
anteed at a frequency of at least fOSG Min.
3. When the OSG is disabled, operation in this
area is guaranteed at the quartz crystal frequency.
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept a fOSG.
4. When the OSG is disabled, operation in this
area is not guaranteed
When the OSG is enabled, access to this area is
prevented. The internal frequency is kept at fOSG.
21/83