ST62P60CM3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST62P60CM3
STMicroelectronics
ST62P60CM3 Datasheet PDF : 83 Pages
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ST6253C ST6263C ST6263B ST6260C ST6260B
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
7
0
- LES ESB GEN -
-
-
-
Bit 5 = ESB: Edge Selection bit.
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt. When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Bit 7, Bits 3-0 = Unused.
Bit 6 = LES: Level/Edge Selection bit.
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Interrupt sources available on these MCUs are
summarized in the Table 9 with associated mask
bit to enable/disable the interrupt request.
Table 9Interrupt Requests and Mask Bits
Peripheral
Register
Address
Register
GENERAL
IOR
C8h
TIMER
TSCR1
D4h
A/D CONVERTER ADCR
D1h
AR TIMER
ARMC
D5h
SPI
Port PAn
Port PBn
Port PCn
SPIMOD
ORPA-DRPA
ORPB-DRPB
ORPC-DRPC
E2h
C0h-C4h
C1h-C5h
C2h-C6h
Mask bit
GEN
ETI
EAI
OVIE
CPIE
EIE
SPIE
ORPAn-DRPAn
ORPBn-DRPBn
ORPCn-DRPCn
Masked Interrupt Source
Interrupt
vector
All Interrupts, excluding NMI
TMZ: TIMER Overflow
Vector 4
EOC: End of Conversion
Vector 4
OVF: AR TIMER Overflow
CPF: Successful compare
EF: Active edge on ARTIMin
Vector 3
SPRUN: End of Transmission Vector 2
PAn pin
Vector 1
PBn pin
Vector 1
PCn pin
Vector 2
32/83
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