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ST7FDALI View Datasheet(PDF) - STMicroelectronics

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ST7FDALI Datasheet PDF : 141 Pages
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ST7DALI
POWER SAVING MODES (Cont’d)
Figure 25. ACTIVE-HALT Timing Overview
ACTIVE 256 OR 4096 CPU
RUN HALT CYCLE DELAY 1)
RUN
HALT
INSTRUCTION
[Active Halt Enabled]
RESET
OR
INTERRUPT
FETCH
VECTOR
Figure 26. ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION
(Active Halt enabled)
(AWUCSR.AWUEN=0)
OSCILLATOR ON
PERIPHERALS 2) OFF
CPU
OFF
I BIT
0
N
RESET
N
Y
INTERRUPT 3)
Y
OSCILLATOR ON
PERIPHERALS 2) OFF
CPU
ON
I BIT
X 4)
256 OR 4096 CPU CLOCK
CYCLE DELAY
OSCILLATOR ON
PERIPHERALS ON
CPU
ON
I BIT
X 4)
FETCH RESET VECTOR
OR SERVICE INTERRUPT
Notes:
1. This delay occurs only if the MCU exits ACTIVE-
HALT mode by means of a RESET.
2. Peripherals clocked with an external clock
source can still be active.
3. Only the RTC1 interrupt and some specific inter-
rupts can exit the MCU from ACTIVE-HALT mode.
Refer to Table 5, “Interrupt Mapping,” on page 35
for more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.
9.6 AUTO WAKE UP FROM HALT MODE
Auto Wake Up From Halt (AWUFH) mode is simi-
lar to Halt mode with the addition of a specific in-
ternal RC oscillator for wake-up (Auto Wake Up
from Halt Oscillator). Compared to ACTIVE-HALT
mode, AWUFH has lower power consumption (the
main clock is not kept running, but there is no ac-
curate realtime clock available.
It is entered by executing the HALT instruction
when the AWUEN bit in the AWUCSR register has
been set.
Figure 27. AWUFH Mode Block Diagram
AWU RC
oscillator
fAWU_RC
to Timer input capture
/64
divider
AWUFH
AWUFH
interrupt
prescaler/1 .. 255 (ei0 source)
As soon as HALT mode is entered, and if the
AWUEN bit has been set in the AWUCSR register,
the AWU RC oscillator provides a clock signal
(fAWU_RC). Its frequency is divided by a fixed divid-
er and a programmable prescaler controlled by the
AWUPR register. The output of this prescaler pro-
vides the delay time. When the delay has elapsed
the AWUF flag is set by hardware and an interrupt
wakes-up the MCU from Halt mode. At the same
time the main oscillator is immediately turned on
and a 256 or 4096 cycle delay is used to stabilize
it. After this start-up delay, the CPU resumes oper-
ation by servicing the AWUFH interrupt. The AWU
flag and its associated interrupt are cleared by
software reading the AWUCSR register.
To compensate for any frequency dispersion of
the AWU RC oscillator, it can be calibrated by
measuring the clock frequency fAWU_RC and then
calculating the right prescaler value. Measurement
mode is enabled by setting the AWUM bit in the
AWUCSR register in Run mode. This connects
fAWU_RC to the input capture of the 12-bit Auto-Re-
load timer, allowing the fAWU_RC to be measured
using the main oscillator clock as a reference time-
base.
42/141
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