AC/DC parameters
PSD8XXFX
Figure 49. ISC timing
TCK
tISCCH
t ISCCL
t ISCPSU tISCPH
TDI/TMS
t ISCPZV
t ISCPCO
ct(s) ISC OUTPUTS/TDO
tISCPVZ
rodu ISC OUTPUTS/TDO
lete P Table 68. ISC timing (5 V devices)
bso Symbol
Parameter
) - O tISCCF
ct(s tISCCH
rodu tISCCL
P tISCCFP
te tISCCHP
ole tISCCLP
bstISCPSU
OtISCPH
Clock (TCK, PC1) frequency (except for
PLD)
Clock (TCK, PC1) high time (except for
PLD)
Clock (TCK, PC1) low time (except for
PLD)
Clock (TCK, PC1) frequency (PLD only)
Clock (TCK, PC1) high time (PLD only)
Clock (TCK, PC1) low time (PLD only)
ISC port setup time
ISC port hold up time
AI02865
Conditions
-70
-90
-15
Unit
Min Max Min Max Min Max
(1)
20
18
14 MHz
(1)
23
26
31
ns
(1)
23
26
31
ns
(2)
2
2
2 MHz
(2)
240
240
240
ns
(2)
240
240
240
ns
7
8
10
ns
5
5
5
ns
tISCPCO ISC port clock to output
21
23
25 ns
tISCPZV ISC port high-impedance to valid output
21
23
25 ns
ISC port valid output to
tISCPVZ high-Impedance
21
23
25 ns
1. For non-PLD Programming, Erase or in ISC by-pass mode.
2. For program or erase PLD only.
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Doc ID 7833 Rev 7