PSD8XXFX
PSD register description and address offset
Table 8. Register address offset (continued)
Register
name
Port A
Port B
Port C
Port D
Other
(1)
Description
Mask
macrocells 22 22
AB
Blocks writing to the Output macrocells
AB
Mask
macrocells
BC
23 23
Blocks writing to the Output macrocells
BC
Primary Flash
Protection
C0
Read only – Primary Flash Sector
Protection
Secondary
) Flash memory
C2
t(s Protection
c JTAG Enable
C7
du PMMR0
B0
ro PMMR2
B4
P Page
E0
lete VM
E2
Obsolete Product(s) - Obso 1. Other registers that are not part of the I/O ports.
Read only – PSD Security and Secondary
Flash memory Sector Protection
Enables JTAG port
Power Management register 0
Power Management register 2
Page register
Places PSD memory areas in program
and/or data space on an individual basis.
Doc ID 7833 Rev 7
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