PSD834F4A-20UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD834F4A-20UI Datasheet PDF : 128 Pages
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PSD8XXFX
PLDS
14.3 Complex PLD (CPLD)
The CPLD can be used to implement system logic functions, such as loadable counters and
shift registers, system mailboxes, handshaking protocols, state machines, and random logic.
The CPLD can also be used to generate three External Chip Select (ECS0-ECS2), routed to
port D.
Although External Chip Select (ECS0-ECS2) can be produced by any Output macrocell
(OMC), these three External Chip Select (ECS0-ECS2) on port D do not consume any
Output macrocells (OMC).
As shown in Figure 12, the CPLD has the following blocks:
● 24 input macrocells (IMC)
● 16 Output macrocells (OMC)
) ● Macrocell Allocator
t(s ● Product Term Allocator
c ● AND Array capable of generating up to 137 product terms
du ● Four I/O ports.
ro Each of the blocks are described in the sections that follow.
P The input macrocells (IMC) and Output macrocells (OMC) are connected to the PSD
te internal data bus and can be directly accessed by the MCU. This enables the MCU software
le to load data into the Output macrocells (OMC) or read data from both the input and Output
o macrocells (IMC and OMC).
bs This feature allows efficient implementation of system logic and eliminates the need to
O connect the data bus to the AND Array as required in most standard PLD macrocell
Obsolete Product(s) - architectures.
Doc ID 7833 Rev 7
51/128
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