PSD854F2A-20MI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD854F2A-20MI Datasheet PDF : 128 Pages
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I/O ports
PSD8XXFX
Table 20. Port operating modes (continued)
Port mode
Port A
Port B
Port C
Port D
Address Out
Address In
Data port
Yes (A7 – 0)
Yes (A7 – 0)
No
No
or (A15 – 8)
Yes
Yes
Yes
Yes
Yes (D7 – 0)
No
No
No
Peripheral I/O
JTAG ISP
Yes
No
No
No
No
No
Yes(1)
No
1. Can be multiplexed with other I/O functions.
) Table 21. Port operating mode settings
uct(s Mode
Defined in
PSDabel
Defined in PSD
configuration
Control Direction
register register
setting setting
VM
register
setting
JTAG Enable
rod MCU I/O
te P PLD I/O
le Data port (Port A)
so Address Out
b (Port A,B)
- O Address In
) (Port A,B,C,D)
t(s Peripheral I/O
c (Port A)
rodu JTAG ISP(3)
Declare pins only
N/A(1)
Logic equations
N/A
N/A
Specify bus type
Declare pins only
N/A
Logic for equation
input macrocells
Logic equations
(PSEL0 & 1)
JTAGSEL
N/A
N/A
JTAG
Configuration
1 = output,
0
0 = input(2)
N/A
N/A
N/A
(2)
N/A
N/A
N/A
N/A
N/A
N/A
1
1(2)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A PIO bit = 1
N/A
N/A
N/A
N/A JTAG_Enable
P 1. N/A = Not Applicable
te 2. The direction of the port A,B,C, and D pins are controlled by the Direction register ORed with the individual output enable
product term (.oe) from the CPLD AND Array.
ole 3. Any of these three methods enables the JTAG pins on port C.
Obs Table 22. I/O port Latched address output assignments
MCU
8051XA (8-Bit)
Port A (PA3-PA0)
N/A(1)
Port A (PA7-PA4)
Address a7-a4
Port B (PB3-PB0)
Address a11-a8
Port B (PB7-PB4)
N/A
80C251
(Page mode)
All Other
8-Bit Multiplexed
8-Bit
Non-Multiplexed bus
N/A
Address a3-a0
N/A
N/A
Address a7-a4
N/A
Address a11-a8
Address a3-a0
Address a3-a0
Address a15-a12
Address a7-a4
Address a7-a4
1. N/A = Not Applicable
70/128
Doc ID 7833 Rev 7
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