PSD833F3A-20UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD833F3A-20UI Datasheet PDF : 128 Pages
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PSD8XXFX
I/O ports
16.19
Enable Out
The Enable Out register can be read by the MCU. It contains the output enable values for a
given port. A 1 indicates the driver is in output mode. A 0 indicates the driver is in tri-state
and the pin is in input mode.
16.20 Ports A and B – functionality and structure
Ports A and B have similar functionality and structure, as shown in Figure 27. The two ports
can be configured to perform one or more of the following functions:
● MCU I/O mode
● CPLD Output – macrocells McellAB7-McellAB0 can be connected to port A or port B.
) McellBC7-McellBC0 can be connected to port B or port C.
t(s ● CPLD input – Via the input macrocells (IMC).
c ● Latched Address output – Provide latched address output as per Table 22.
u ● Address In – Additional high address inputs using the input macrocells (IMC).
rod ● Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew
rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain mode.
te P ● Data port – port A to D7-D0 for 8 bit non-multiplexed bus
le ● Multiplexed Address/Data port for certain types of MCU bus interfaces.
o ● Peripheral mode – port A only
bs Figure 27. Port A and port B structure
t(s) - O WR
ADDRESS
uc ALE
DATA OUT
REG.
DQ
DQ
G
dMACROCELL OUTPUTS
ro READ MUX
PP
te D
le B
o CONTROL REG.
s DQ
Ob WR
DATA OUT
ADDRESS
A[ 7:0] OR A[15:8]
OUTPUT
MUX
DATA IN
OUTPUT
SELECT
ENABLE OUT
PORT
A OR B PIN
DIR REG.
DQ
WR
ENABLE PRODUCT TERM (.OE)
INPUT
MACROCELL
CPLD - INPUT
AI02887
Doc ID 7833 Rev 7
75/128
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