PSD814F3VA-15M View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
PSD814F3VA-15M Datasheet PDF : 128 Pages
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PSD8XXFX
Power management
Table 31. Power Management mode registers PMMR0(1) (continued)
Bit
Name
Description
Bit 4
0=
on
PLD Array clk
1=
off
CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo Bit is ’0.’
CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
Bit 5
0=
on
PLD MCell clk
1=
off
CLKIN (PD1) input to the PLD macrocells is connected.
CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
Bit 6 X
0
Not used, and should be set to zero.
) Bit 7 X
0
Not used, and should be set to zero.
t(s 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the
c registers.
rodu Table 32. Power Management mode registers PMMR2(1)
P Bit
Name
Description
te Bit 0
le Bit 1
bso Bit 2
X
X
PLD Array
CNTL0
t(s) - O Bit 3
PLD Array
CNTL1
uc Bit 4
PLD Array
CNTL2
Prod Bit 5
PLD Array
ALE
lete Bit 6
so Bit 7
PLD Array
DBE
X
0
Not used, and should be set to zero.
0
Not used, and should be set to zero.
0 = on Cntl0 input to the PLD AND Array is connected.
1 = off Cntl0 input to PLD AND Array is disconnected, saving power.
0 = on Cntl1 input to the PLD AND Array is connected.
1 = off Cntl1 input to PLD AND Array is disconnected, saving power.
0 = on Cntl2 input to the PLD AND Array is connected.
1 = off Cntl2 input to PLD AND Array is disconnected, saving power.
0 = on ALE input to the PLD AND Array is connected.
1 = off ALE input to PLD AND Array is disconnected, saving power.
0 = on DBE input to the PLD AND Array is connected.
1 = off DBE input to PLD AND Array is disconnected, saving power.
0
Not used, and should be set to zero.
Ob1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the
registers.
Doc ID 7833 Rev 7
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