PSD834F5VA-12JIT View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

PSD834F5VA-12JIT

Flash in-system programmable (ISP) ipherals for 8-bit MCUs, 5 V

STMicroelectronics 

Reset timing and device status at reset

Figure 33. Reset (RESET) timing

PSD8XXFX

VCC

RESET

VCC(min)

tNLNH-PO

Power-On Reset

tOPR

tNLNH

tNLNH-A

Warm Reset

tOPR

AI02866b

Table 34. Status during Power-on reset, Warm reset and Power-down mode

) Port configuration

Power-on reset

Warm reset

Power-down mode

t(s MCU I/O

duc PLD Output

Pro Address Out

te Data port

ole Peripheral I/O

Input mode

Valid after internal PSD

configuration bits are

loaded

Tri-stated

Tri-stated

Tri-stated

Input mode

Valid

Tri-stated

Tri-stated

Tri-stated

Unchanged

Depends on inputs to PLD

(addresses are blocked in

PD mode)

Not defined

Tri-stated

Tri-stated

Obs Register

Power-on reset

Warm reset

Power-down mode

) - PMMR0 and PMMR2

t(s Macrocells flip-flop status

roduc VM register(1)

te P All other registers

Cleared to '0'

Cleared to '0' by internal

Power-On Reset

Initialized, based on the

selection in PSDsoft

Configuration menu

Cleared to '0'

Unchanged

Depends on .re and .pr

equations

Initialized, based on the

selection in PSDsoft

Configuration menu

Cleared to '0'

Unchanged

Depends on .re and .pr

equations

Unchanged

Unchanged

Obsole 1. The SR_cod and Periphmode bits in the VM register are always cleared to '0' on Power-on reset or Warm reset.

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Doc ID 7833 Rev 7

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