M38C2XMX View Datasheet(PDF) - MITSUBISHI ELECTRIC

Part Name

Description

Manufacturer

M38C2XMX

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

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MITSUBISHI MICROCOMPUTERS

38C2 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

WATCHDOG TIMER

The watchdog timer gives a mean of returning to the reset status

when a program cannot run on a normal loop (for example, because

of a software run-away). The watchdog timer consists of an 8-bit

counter.

Initial Value of Watchdog Timer

At reset or writing to the watchdog timer control register, each watch-

dog timer is set to “FF16.” Instructions such as STA, LDM and CLB to

generate the write signals can be used.

The written data in bits 0 to 5 are not valid, and the above values are

set.

Standard Operation of Watchdog Timer

The watchdog timer is in the stop state at reset and the watchdog

timer starts to count down by writing an optional value in the watch-

dog timer control register. An internal reset occurs at an underflow of

the watchdog timer. Then, reset is released after the reset release

time is elapsed, the program starts from the reset vector address.

Normally, writing to the watchdog timer control register before an

underflow of the watchdog timer is programmed. If writing to the watch-

dog control register is not executed, the watchdog timer does not

operate.

When reading the watchdog timer control register is executed, the

contents of the high-order 6-bit counter and the STP instruction dis-

able bit (bit 6), and the count source selection bit (bit 7) are read out.

When the STP instruction disable bit is “0”, the STP instruction is

valid. The STP instruction is disabled by writing to “1” to this bit. In

this time, when the STP instruction is executed, it is handled as the

undefined instruction, the internal reset occurs. This bit cannot be

cleared to “0” by program. This bit is “0” after reset.

The time until the underflow of the watchdog timer control register

after writing to the watchdog timer control register is executed is as

follows (when the bit 7 of the watchdog timer control register is “0”) ;

• at through, frequency/2/4/8 mode (f(XIN)) = 8 MHz): 32.768 ms

• at low-speed mode (f(XCIN) = 32 KHz): 8.19s

s Note

The watchdog timer continues to count even during the wait time set

by timer 1 and timer 2 to release the stop state and in the wait mode.

Accordingly, do not underflow the watchdog timer in this time.

XCIN

Watchdog timer H

count source

selection bit

“1”

System clock control

1/1024

“0”

bit (bit 6)

“0”

XIN

1/4

“1”

Undefined instruction

Reset

STP instruction disable bit

Watchdog timer

L (2)

STP instruction

RESETIN

Watchdog timer

H (6)

Reset

circuit

Wait until reset release

Data bus

“FF16” is set when

watchdog timer

control register is

written to.

Internal reset

Fig. 42 Block diagram of Watchdog timer

b7

Fig. 43 Structure of Watchdog timer control register

b0

Watchdog timer control register

(WDTCON : address 003716)

Watchdog timer H (for read-out of high-order 6 bit)

“FF16” is set to watchdog timer by writing to these bits.

STP instruction disable bit

0: STP instruction enabled

1: STP instruction disabled

Watchdog timer count source selection bit

0: 1/1024 of system clock

1: 1/4 of system clock

f(XIN)

Internal reset

signal

Watchdog timer detected

Fig. 44 Timing diagram of reset output

≈ 32msec (at f(XIN)=8MHZ)

44

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