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PIC32MX220F032B-I/SO View Datasheet(PDF) - Microchip Technology

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Description
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PIC32MX220F032B-I/SO Datasheet PDF : 321 Pages
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PIC32MX1XX/2XX
REGISTER 9-1: DMACON: DMA CONTROLLER CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
U-0
U-0
31:24
U-0
U-0
23:16
R/W-0
U-0
15:8
ON(1)
U-0
U-0
7:0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
SUSPEND DMABUSY
U-0
U-0
U-0
U-0
Bit
25/17/9/1
U-0
U-0
U-0
U-0
Bit
24/16/8/0
U-0
U-0
U-0
U-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0
bit 15 ON: DMA On bit(1)
1 = DMA module is enabled
0 = DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0
bit 12 SUSPEND: DMA Suspend bit
bit 11
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally
DMABUSY: DMA Module Busy bit(4)
1 = DMA module is active
0 = DMA module is disabled and not actively transferring data
bit 10-0 Unimplemented: Read as ‘0
Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS61168C-page 106
Preliminary
© 2011 Microchip Technology Inc.

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