PIC32MX250F128C-I/SO View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX250F128C-I/SO

32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX

REGISTER 17-1: I2CXCON: I2C™ CONTROL REGISTER

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

31:24

23:16

15:8

7:0

U-0

—

U-0

—

R/W-0

ON(1)

R/W-0

GCEN

U-0

—

U-0

—

U-0

—

R/W-0

STREN

U-0

—

U-0

—

R/W-0

SIDL

R/W-0

ACKDT

U-0

—

U-0

—

R/W-1, HC

SCLREL

R/W-0, HC

ACKEN

U-0

—

U-0

—

R/W-0

STRICT

R/W-0, HC

RCEN

U-0

—

U-0

—

R/W-0

A10M

R/W-0, HC

PEN

Bit

25/17/9/1

U-0

—

U-0

—

R/W-0

DISSLW

R/W-0, HC

RSEN

Bit

24/16/8/0

U-0

—

U-0

—

R/W-0

SMEN

R/W-0, HC

SEN

Legend:

R = Readable bit

-n = Value at POR

HC = Cleared in Hardware

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: I2C Enable bit(1)

1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins

0 = Disables the I2C module; all I2C pins are controlled by PORT functions

bit 14 Unimplemented: Read as ‘0’

bit 13

bit 12

SIDL: Stop in Idle Mode bit

1 = Discontinue module operation when device enters Idle mode

0 = Continue module operation in Idle mode

SCLREL: SCLx Release Control bit (when operating as I2C slave)

1 = Release SCLx clock

0 = Hold SCLx clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at

beginning of slave transmission. Hardware clear at end of slave reception.

bit 11

If STREN = 0:

Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave

transmission.

STRICT: Strict I2C Reserved Address Rule Enable bit

1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate

addresses in reserved address space.

0 = Strict I2C Reserved Address Rule not enabled

bit 10

A10M: 10-bit Slave Address bit

1 = I2CxADD is a 10-bit slave address

0 = I2CxADD is a 7-bit slave address

bit 9

DISSLW: Disable Slew Rate Control bit

1 = Slew rate control disabled

0 = Slew rate control enabled

bit 8

SMEN: SMBus Input Levels bit

1 = Enable I/O pin thresholds compliant with SMBus specification

0 = Disable SMBus input thresholds

Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the

SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

© 2011 Microchip Technology Inc.

Preliminary

DS61168C-page 175

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