PIC32MX120F032B-V/SP View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC32MX120F032B-V/SP
Microchip Technology
PIC32MX120F032B-V/SP Datasheet PDF : 321 Pages
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PIC32MX1XX/2XX
REGISTER 26-7: WDTCON: WATCHDOG TIMER CONTROL REGISTER(1,2,3)
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0
U-0
31:24
—
—
U-0
U-0
23:16
—
—
R/W-0
U-0
15:8
ON(1,2)
—
U-0
R-y
7:0
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
R-y
R-y
R-y
SWDTPS<4:0>
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
U-0
U-0
U-0
—
—
—
R-y
R/W-0
R/W-0
WDTWINEN WDTCLR
Legend:
R = Readable bit
-n = Value at POR
y = Values set from Configuration bits on POR
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 ON: Watchdog Timer Enable bit(1,2)
1 = Enables the WDT if it is not enabled by the device configuration
0 = Disable the WDT if it was enabled in software
bit 14-7 Unimplemented: Read as ‘0’
bit 6-2 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits
On reset, these bits are set to the values of the WDTPS <4:0> of Configuration bits.
bit 1
WDTWINEN: Watchdog Timer Window Enable bit
1 = Enable windowed Watchdog Timer
0 = Disable windowed Watchdog Timer
bit 0
WDTCLR: Watchdog Timer Reset bit
1 = Writing a ‘1’ will clear the WDT
0 = Software cannot force this bit to a ‘0’
Note 1: A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software.
2: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
DS61168C-page 236
Preliminary
© 2011 Microchip Technology Inc.
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