PIC32MX230F064B-I/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC32MX230F064B-I/SS

32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

Microchip Technology 

PIC32MX1XX/2XX

FIGURE 29-11:

SCKX

(CKP = 0)

SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS

SP36

SP11

SP10

SP21

SP20

SCKX

(CKP = 1)

SP35

SP20

SP21

SDOX

MSb

Bit 14 - - - - - -1

SP30,SP31

SDIX

SP40

MSb In

SP41

Bit 14 - - - -1

Note: Refer to Figure 29-1 for load conditions.

LSb

LSb In

TABLE 29-27: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V

(unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +105°C for V-temp

Param.

No.

Symbol

Characteristics(1)

Min. Typ.(2) Max. Units

Conditions

SP10 TSCL

SCKx Output Low Time (Note 3) TSCK/2

—

—

ns

—

SP11 TSCH

SCKx Output High Time (Note 3) TSCK/2

—

—

ns

—

SP20 TSCF

SCKx Output Fall Time (Note 4)

—

—

—

ns See parameter DO32

SP21 TSCR

SCKx Output Rise Time (Note 4) —

—

—

ns See parameter DO31

SP30 TDOF

SDOx Data Output Fall Time

(Note 4)

—

—

—

ns See parameter DO32

SP31 TDOR

SDOx Data Output Rise Time

(Note 4)

—

—

—

ns See parameter DO31

SP35 TSCH2DOV, SDOx Data Output Valid after

TSCL2DOV SCKx Edge

—

—

15

ns VDD > 2.7V

—

—

20

ns VDD < 2.7V

SP36 TDOV2SC, SDOx Data Output Setup to

15

—

—

ns

—

TDOV2SCL First SCKx Edge

SP40 TDIV2SCH, Setup Time of SDIx Data Input to 15

—

—

ns VDD > 2.7V

TDIV2SCL SCKx Edge

20

—

—

ns VDD < 2.7V

SP41 TSCH2DIL, Hold Time of SDIx Data Input

TSCL2DIL to SCKx Edge

15

—

—

ns VDD > 2.7V

20

—

—

ns VDD < 2.7V

Note 1: These parameters are characterized, but not tested in manufacturing.

2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPIx pins.

DS61168C-page 264

Preliminary

© 2011 Microchip Technology Inc.

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