PIC32MX1XX/2XX
FIGURE 8-1:
PIC32MX1XX/2XX FAMILY CLOCK DIAGRAM
USB PLL(5)
UFIN
div x
PLL x24
UFIN = 4 MHz
UPLLIDIV<2:0>
USB Clock (48 MHz)
div 2
UFRCEN
UPLLEN
REFCLKI
System USB PLL
4 MHz ≤ FIN ≤ 5 MHz
FIN
div x
PLL
POSC
FRC
LPRC
SOSC
PBCLK
SYSCLK
div N
OE
REFCLKO
RODIV<14:0>
To SPI
FPLLIDIV<2:0>
ROSEL<3:0>
Primary Oscillator
(POSC)
COSC<2:0>
PLLMULT<2:0>
div y
XTPLL, HSPLL,
ECPLL, FRCPLL
PLLODIV<2:0>
C1(3)
OSC1
XTAL
RF(2)
RS(1)
C2(3) OSC2(4)
To Internal
Logic
Enable
div 2
POSC (XT, HS, EC)
div 16
FRC
FRC/16
Postscaler Peripherals
div x
PBCLK (TPB)
PBDIV<1:0>
To ADC
FRC
Oscillator
8 MHz typical
Postscaler
FRCDIV
CPU and Select Peripherals
SYSCLK
TUN<5:0>
FRCDIV<2:0>
LPRC
Oscillator
31.25 kHz typical
LPRC
Secondary Oscillator (SOSC)
SOSCO
32.768 kHz
SOSCEN and FSOSCEN
SOSCI
SOSC
Clock Control Logic
Fail-Safe
Clock
Monitor
FSCM INT
FSCM Event
NOSC<2:0>
COSC<2:0>
FSCMEN<1:0>
OSWEN
WDT, PWRT
Notes: 1.
2.
3.
4.
5.
Timer1, RTCC
A series resistor, RS, may be required for AT strip cut crystals.
The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ.
Refer to Section 6. “Oscillator Configuration” (DS61112) in the “PIC32 Family Reference Manual” for help in determining the best
oscillator components.
PBCLK out is available on the OSC2 pin in certain clock modes.
USB PLL is available on PIC32MX2XX devices only.
DS61168C-page 96
Preliminary
© 2011 Microchip Technology Inc.