STM32F302xx/STM32F303xx
Electrical characteristics
Figure 24. Recommended NRST pin protection
%XTERNAL
RESET CIRCUIT
6$$
.234
205
&
)NTERNAL 2ESET
&ILTER
6.3.16
-36
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 55. Otherwise the reset will not be taken into account by the device.
Timer characteristics
Symbol
Parameter
Conditions Min Typ
Max Unit
VIL(NPOR)(1) NPOR Input low level voltage
VIH(NPOR)(1) NPOR Input high level voltage
0.5VDDA
+ 0.2
0.475VDDA
- 0.2
V
Vhys(NPOR)(1)
NPOR Schmitt trigger voltage
hysteresis
200
mV
RPU
Weak pull-up equivalent resistor(2) VIN = VSS
25
40
55
kΩ
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order).
The parameters given in Table 56 are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 56. TIMx(1) characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tres(TIM)(2) Timer resolution time
fTIMxCLK = 72 MHz
(except TIM1/8)
fTIMxCLK = 144 MHz,
x= 1.8
fEXT(2)
ResTIM(2)
Timer external clock
frequency on CH1 to CH4
Timer resolution
fTIMxCLK = 72 MHz
TIMx (except TIM2)
TIM2
1
13.9
6.95
0
0
-
-
-
tTIMxCLK
-
ns
-
fTIMxCLK/2
36
16
32
ns
MHz
MHz
bit
Doc ID 023353 Rev 5
93/133