TC850
Internal
Clock
Busy
.......
.....
1280 Internal Clock Cycles
836 Clock Cycles
DB0-DB7
FIGURE 8-6:
Data Meaningless
Conversion Timing, Continuous Mode
.....
443-1/2 Clock
Cycles
Data Valid
1/2 Clock Cycle
Data Meaningless
CONT/DEMAND
BUSY
RD
TWRE
TRE
TWRD
DB0-DB7
HI-Z
NOTES: CS = HIGH; CE = LOW
Data Bits 8-14
Polarity
Data Bits 0-7
Data Bits 8-14
Overrange
High-Impedance
State
FIGURE 8-7:
Bus Output Timing, Continuous Mode
© 2006 Microchip Technology Inc.
DS21479C-page 19