ST72F324J4TCTRS View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324J4TCTRS

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

On-chip peripherals

Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status.

When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the

T8 bit in the SCICR1 register.

Character transmission

During an SCI transmission, data shifts out LSB first on the TDO pin. In this mode, the

SCIDR register consists of a buffer (TDR) between the internal bus and the transmit shift

register (see Figure 55).

Procedure

1. Select the M bit to define the word length.

2. Select the desired baud rate using the SCIBRR and the SCIETPR registers.

) 3. Set the TE bit to assign the TDO pin to the alternate function and to send a idle frame

t(s as first transmission.

c 4. Access the SCISR register and write the data to send in the SCIDR register (this

du sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted.

ro Clearing the TDRE bit is always performed by the following software sequence:

P 1. An access to the SCISR register

te 2. A write to the SCIDR register

le The TDRE bit is set by hardware and it indicates:

so ● The TDR register is empty.

b ● The data transfer is beginning.

- O ● The next data can be written in the SCIDR register without overwriting the previous

) data.

t(s This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR

c register.

du When a transmission is taking place, a write instruction to the SCIDR register stores the

ro data in the TDR register and which is copied in the shift register at the end of the current

P transmission.

teWhen no transmission is taking place, a write instruction to the SCIDR register places the

ledata directly in the shift register, the data transmission starts, and the TDRE bit is

o immediately set.

s When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt

Ob is generated if the TCIE is set and the I bit is cleared in the CCR register.

Clearing the TC bit is performed by the following software sequence:

1. An access to the SCISR register

2. A write to the SCIDR register

Note:

The TDRE and TC bits are cleared by the same software sequence.

Doc ID 13841 Rev 1

115/193

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