ST72F324J6TCX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324J6TCX

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

On-chip peripherals

ST72324xx-Auto

Table 62. SCISR register description

Bit Name

Function

Transmit Data Register Empty

This bit is set by hardware when the content of the TDR register has been transferred

7 TDRE

into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2

register. It is cleared by a software sequence (an access to the SCISR register

followed by a write to the SCIDR register).

0: Data is not transferred to the shift register.

1: Data is transferred to the shift register.

Note: Data will not be transferred to the shift register unless the TDRE bit is cleared.

Transmission Complete

duct(s) 6 TC

This bit is set by hardware when transmission of a frame containing data is complete.

An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a

software sequence (an access to the SCISR register followed by a write to the

SCIDR register).

0: Transmission is not complete

1: Transmission is complete

Note: TC is not set after the transmission of a Preamble or a Break.

ro Received Data Ready Flag

bsolete P 5 RDRF

This bit is set by hardware when the content of the RDR register has been

transferred to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2

register. It is cleared by a software sequence (an access to the SCISR register

followed by a read to the SCIDR register).

0: Data is not received

1: Received data is ready to be read

O Idle line detect

roduct(s) - 4 IDLE

This bit is set by hardware when a Idle Line is detected. An interrupt is generated if

the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access

to the SCISR register followed by a read to the SCIDR register).

0: No idle line is detected

1: Idle line is detected

Note: The IDLE bit is not reset until the RDRF bit has itself been set (that is, a new

idle line occurs).

P Overrun error

te This bit is set by hardware when the word currently being received in the shift register

bsole3 OR

is ready to be transferred into the RDR register while RDRF = 1. An interrupt is

generated if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an

access to the SCISR register followed by a read to the SCIDR register).

0: No overrun error

O 1: Overrun error is detected

Note: When this bit is set RDR register content is not lost but the shift register is

overwritten.

Noise Flag

2 NF

This bit is set by hardware when noise is detected on a received frame. It is cleared

by a software sequence (an access to the SCISR register followed by a read to the

SCIDR register).

0: No noise is detected

1: Noise is detected

Note: This bit does not generate interrupt as it appears at the same time as the

RDRF bit which itself generates an interrupt.

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Doc ID 13841 Rev 1

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