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ST72F324J2TCRS View Datasheet(PDF) - STMicroelectronics

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Description
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ST72F324J2TCRS Datasheet PDF : 194 Pages
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ST72324xx-Auto
Electrical characteristics
Table 97. PLL characteristics
Symbol
Parameter
Δ fCPU/fCPU Instantaneous PLL jitter(1)
1. Data characterized but not tested
Conditions
fOSC = 4 MHz
fOSC = 2 MHz
Min Typ Max Unit
1.0 2.5
%
2.5 4.0
The user must take the PLL jitter into account in the application (for example, in serial
communication or sampling of high frequency signals). The PLL jitter is a periodic effect,
which is integrated over several CPU cycles. Therefore the longer the period of the
application signal, the less it will be impacted by the PLL jitter.
Figure 70 shows the PLL jitter integrated on application signals in the range 125 kHz to
) 2 MHz. At frequencies of less than 125 kHz, the jitter is negligible.
ct(s Figure 70. Integrated PLL jitter vs signal frequency(1)
du +/-Jitter (%)
ro 1.2
1
P 0.8
FLASH typ
ROM max
ROM typ
te 0.6
le 0.4
o 0.2
bs 0
4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz
OApplication Frequency
t(s) - 1. Measurement conditions: fCPU = 8 MHz
duc 12.7
Obsolete Pro 12.7.1
Memory characteristics
RAM and hardware registers
Table 98. RAM and hardware registers
Symbol
Parameter
Conditions
VRM Data retention mode(1)
Halt mode (or Reset)
Min Typ Max Unit
1.6
V
1. Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in
hardware registers (only in Halt mode). Not tested in production.
12.7.2
Flash memory
Table 99. Dual voltage HDFlash memory
Symbol
Parameter
Conditions
fCPU
VPP
Operating frequency
Programming voltage(2)
Read mode
Write/Erase mode
4.5V < VDD < 5.5V
Min(1) Typ Max(1) Unit
0
8
MHz
1
8
11.4
12.6 V
Doc ID 13841 Rev 1
157/193

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