ST72F324J6TCX View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324J6TCX

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

Electrical characteristics

Figure 79. RESET pin protection when LVD is enabled(1)(2)(3)(4)(5)(6)(7)

VDD

ST72XXX

External

reset

Recommended Optional

(note 6)

0.01µF 1MΩ

RON

Filter

Pulse

generator

Internal

reset

Watchdog

LVD reset

1. The reset network protects the device against parasitic resets.

) 2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.

t(s Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

c 3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin

u can go below the VIL max. level specified in Section 12.10.1. Otherwise the reset will not be taken into

account internally.

rod 4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user

must ensure that the current sunk on the RESET pin (by an external pull-up for example) is less than the

P absolute maximum value specified for IINJ(RESET) in Section 12.2.2 on page 148.

5. When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-down capacitor is

te recommended to filter noise on the reset line.

le 6. In case a capacitive power supply is used, it is recommended to connect a 1M ohm pull-down resistor to

the RESET pin to discharge any residual voltage induced by this capacitive power supply (this will add 5µA

o to the power consumption of the MCU).

bs 7. Tips when using the LVD:

A. Check that all recommendations related to reset circuit have been applied (see notes above)

O B. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709.

- If this cannot be done, it is recommended to put a 100nF + 1M ohm pull-down on the RESET pin.

C. The capacitors connected on the RESET pin and also the power supply are key to avoiding any start-up

) marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: Replace

t(s 10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.

c Figure 80. RESET pin protection when LVD is disabled(1)(2)(3)(4)

te Produ User

le external

reset

Obso circuit

VDD

4.7kΩ

0.01µF

VDD

RON

Filter

Pulse

generator

ST72XXX

Internal

reset

Watchdog

Required

1. The reset network protects the device against parasitic resets.

2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.

Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin

can go below the VIL max. level specified in Section 12.10.1. Otherwise the reset will not be taken into

account internally.

4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user

must ensure that the current sunk on the RESET pin (by an external pull-up for example) is less than the

absolute maximum value specified for IINJ(RESET) in Section 12.2.2 on page 148.

Doc ID 13841 Rev 1

167/193

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