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ST72F324J2TCRE View Datasheet(PDF) - STMicroelectronics

Part Name
Description
Manufacturer
ST72F324J2TCRE Datasheet PDF : 194 Pages
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Electrical characteristics
ST72324xx-Auto
1. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
2. For Flash devices: Injecting negative current on any of the analog input pins significantly reduces the accuracy of any
conversion being performed on any analog input. Analog pins of ST72F324 devices can be protected against negative
injection by adding a Schottky diode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy
especially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for
IINJ(PIN) and ΣIINJ(PIN) in Section 12.9 does not affect the ADC accuracy.
Figure 85. RAIN max. vs fADC with CAIN = 0pF(1) Figure 86. Recommended CAIN and RAIN
values(2)
45
40
) 35
t(s 30
25
20
c 15
u 10
d 5
ro 0
P 0
2 MHz
1 MHz
10
30
70
CPARASITIC (pF)
1000
100
10
1
0.1
0.01
Cain 10 nF
Cain 22 nF
Cain 47 nF
0.1
1
10
fAIN(KHz)
lete 1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad
o capacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
bs 2. This graph shows that, depending on the input signal variation (fAIN), CAIN can be increased for stabilization time and
decreased to allow the use of a larger serial resistor (RAIN).
- O Figure 87. Typical A/D converter application
Product(s) VAIN
RAIN
AINx
CAIN
VDD
VT
0.6V
VT
0.6V
ST72XXX
2kΩ (max)
Ilkg
10-bit A/D
conversion
CADC
12pF
Obsolete 12.13.1 Analog power supply and reference pins
Depending on the MCU pin count, the package may feature separate VAREF and VSSA
analog power supply pins. These pins supply power to the A/D converter cell and function
as the high and low reference voltages for the conversion. In some packages, VAREF and
VSSA pins are not available (refer to Section 2 on page 15). In this case the analog supply
and reference pads are internally bonded to the VDD and VSS pins.
Separation of the digital and analog power pins allow board designers to improve A/D
performance. Conversion accuracy can be impacted by voltage drops and noise in the event
of heavily loaded or badly decoupled power supply lines (see Section 12.13.2: General PCB
design guidelines).
172/193
Doc ID 13841 Rev 1

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