ST72F324J4TCX View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72F324J4TCX
STMicroelectronics
ST72F324J4TCX Datasheet PDF : 194 Pages
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Supply, reset and clock management
ST72324xx-Auto
6.6
6.6.1
SI registers
System integrity (SI) control/status register (SICSR)
SICSR
7
Res
-
6
AVDIE
R/W
5
AVDF
RO
4
LVDRF
R/W
Reset value: 000x 000x (00h)
3
2
1
0
Reserved
WDGRF
-
R/W
Table 12. SICSR register description
) Bit Name
Function
t(s 7
- Reserved, must be kept cleared
uc Voltage Detector Interrupt Enable
rod This bit is set and cleared by software. It enables an interrupt to be generated
P 6 AVDIE
when the AVDF flag changes (toggles). The pending interrupt information is
automatically cleared when software enters the AVD interrupt routine
te 0: AVD interrupt disabled
1: AVD interrupt enabled
ole Voltage Detector Flag
s This read-only bit is set and cleared by hardware. If the AVDIE bit is set, an
Ob 5 AVDF
interrupt request is generated when the AVDF bit changes value. Refer to
Figure 15 and to Section 6.5.2: AVD (auxiliary voltage detector) for additional
- details.
) 0: VDD over VIT+(AVD) threshold
t(s 1: VDD under VIT-(AVD) threshold
c LVD Reset Flag
Produ 4 LVDRF
This bit indicates that the last reset was generated by the LVD block. It is set by
hardware (LVD reset) and cleared by software (writing zero). See WDGRF flag
description for more details. When the LVD is disabled by option byte, the LVDRF
bit value is undefined.
te3:1
- Reserved, must be kept cleared
le Watchdog Reset Flag
Obso 0 WDGRF
This bit indicates that the last reset was generated by the Watchdog peripheral. It is
set by hardware (watchdog reset) and cleared by software (writing zero) or an LVD
reset (to ensure a stable cleared state of the WDGRF flag when CPU starts).
Combined with the LVDRF information, the flag description is given in Table 13.
Table 13.
Reset source flags
Reset sources
External RESET pin
Watchdog
LVD
LVDRF
0
0
1
WDGRF
0
1
X
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Doc ID 13841 Rev 1
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