ST72F324J2TCRE View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72F324J2TCRE

8-bit MCU for automotive, 3.8 to 5.5V operating range with 8 to 32 Kbyte Flash, 10-bit ADC, 4 timers, SPI, SCI

STMicroelectronics 

ST72324xx-Auto

Interrupts

7.5.2

They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and

PUSH/POP instructions (see Table 18: Dedicated interrupt instruction set).

Interrupt software priority registers (ISPRx)

ISPRx

Reset value: 1111 1111 (FFh)

7

6

5

4

3

2

1

0

ISPR0 I1_3

I0_3

I1_2

I0_2

I1_1

I0_1

I1_0

I0_0

ISPR1 I1_7

I0_7

I1_6

I0_6

I1_5

I0_5

I1_4

I0_4

ISPR2

uct(s) ISPR3

I1_11

R/W

1

RO

I0_11

R/W

1

RO

I1_10

R/W

1

RO

I0_10

R/W

1

RO

I1_9

R/W

I1_13

R/W

I0_9

R/W

I0_13

R/W

I1_8

R/W

I1_12

R/W

I0_8

R/W

I0_12

R/W

Prod These four registers contain the interrupt software priority of each interrupt vector.

te ● Each interrupt vector (except reset and TRAP) has corresponding bits in these

le registers where its own software priority is stored. This correspondence is shown in the

following Table 17.

roduct(s) - Obso Table 17.

ISPRx interrupt vector correspondence

Vector address

ISPRx bits

FFFBh-FFFAh

I1_0 and I0_0 bits

FFF9h-FFF8h

I1_1 and I0_1 bits

...

...

FFE1h-FFE0h

I1_13 and I0_13 bits

te P ● Each I1_x and I0_x bit value in the ISPRx registers has the same meaning as the I1

and I0 bits in the CC register.

ole● Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value

s is kept (for example, previous value = CFh, write = 64h, result = 44h).

Ob The reset, and TRAP vectors have no software priorities. When one is serviced, the I1 and

I0 bits of the CC register are both set.

Caution:

If the I1_x and I0_x bits are modified while the interrupt x is executed the following behavior

has to be considered: If the interrupt x is still pending (new interrupt or flag not cleared) and

the new software priority is higher than the previous one, the interrupt x is re-entered.

Otherwise, the software priority stays unchanged up to the next interrupt request (after the

IRET of the interrupt x).

Table 18. Dedicated interrupt instruction set(1)

Instruction

New description

Function/example I1 H I0 N Z C

HALT

Entering Halt mode

1

0

Doc ID 13841 Rev 1

47/193

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