ST72F324K4TATXE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST72F324K4TATXE
STMicroelectronics
ST72F324K4TATXE Datasheet PDF : 194 Pages
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Power saving modes
ST72324xx-Auto
Figure 25. Active Halt mode flowchart
Halt instruction
(MCCSR.OIE = 1)
N
Interrupt(2)
Y
Oscillator
on
Peripherals(1)
off
CPU
off
I[1:0] bits
10
N
Reset
Y
Oscillator
Peripherals
CPU
I[1:0] bits
on
off
on
XX(3)
Obsolete Product(s) - Obsolete Product(s) 8.4.2
256 or 4096 CPU clock
cycle delay
Oscillator
Peripherals
CPU
I[1:0] bits
on
on
on
XX(3)
Fetch reset vector
or service interrupt
1. Peripheral clocked with an external clock source can still be active.
2. Only the MCC/RTC interrupt and some specific interrupts can exit the MCU from Active Halt mode (such as
external interrupt). Refer to Table 25: Interrupt mapping on page 52 for more details.
3. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
set to the current software priority level of the interrupt routine and restored when the CC register is
popped.
Halt mode
The Halt mode is the lowest power consumption mode of the MCU. It is entered by
executing the ‘HALT’ instruction when the OIE bit of the Main Clock Controller Status
register (MCCSR) is cleared (see Section 10.2: Main clock controller with real-time clock
and beeper (MCC/RTC) on page 70 for more details on the MCCSR register).
The MCU can exit Halt mode on reception of either a specific interrupt (see Table 25:
Interrupt mapping) or a reset. When exiting Halt mode by means of a reset or an interrupt,
the oscillator is immediately turned on and the 256 or 4096 CPU cycle delay is used to
stabilize the oscillator. After the start up delay, the CPU resumes operation by servicing the
interrupt or by fetching the reset vector which woke it up (see Figure 27).
When entering Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to enable
interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,
including the operation of the on-chip peripherals. All peripherals are not clocked except the
ones which get their clock supply from another clock generator (such as an external or
auxiliary oscillator).
The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”
option bit of the option byte. The HALT instruction, when executed while the Watchdog
system is enabled, can generate a Watchdog reset (see Section 14.1 on page 178 for more
details).
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Doc ID 13841 Rev 1
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