ST72324xx-Auto
On-chip peripherals
Figure 30. Watchdog block diagram
fOSC2
MCC/RTC
Div 64
Reset
WDGA T6
Watchdog Control register (WDGCR)
T5 T4 T3 T2 T1 T0
6-bit downcounter (CNT)
12-bit MCC
RTC counter
MSB
LSB
TB[1:0] bits
(MCCSR
) 11
65
0 register)
WDG prescaler
Div 4
uct(s 10.1.4
solete Prod Caution:
How to program the Watchdog timeout
Figure 31 shows the linear relationship between the 6-bit value to be loaded in the
Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be
used for a quick calculation without taking the timing variations into account. If more
precision is needed, use the formulae in Figure 32.
When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Ob Figure 31. Approximate timeout duration
) - 3F
ct(s 38
rodu 30
P28
lete 20
Obso 18
10
08
00
1.5
18
34
50
65
82
98
Watchdog timeout (ms) @ 8 MHz. fOSC2
114
128
Doc ID 13841 Rev 1
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