ST72324xx-Auto
On-chip peripherals
Figure 48. Serial peripheral interface block diagram
SPIDR
Data/Address bus
Read
Read Buffer
Interrupt
request
MOSI
MISO
8-bit Shift Register
7
SPIF WCOL OVR MODF 0
SPICSR 0
SOD SSM SSI
Write
t(s) SCK
SOD
bit
bsolete Produc SS
Master
control
Serial clock
generator
SPI
state
control
1
SS
0
7
SPICR 0
SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
) - O Functional description
t(s A basic example of interconnections between a single master and a single slave is
uc illustrated in Figure 49.
d The MOSI pins are connected together and the MISO pins are connected together. In this
ro way data is transferred serially between master and slave (most significant bit first).
P The communication is always initiated by the master. When the master device transmits
tedata to a slave device via MOSI pin, the slave device responds by sending data to the
lemaster device via the MISO pin. This implies full duplex communication with both data out
o and data in synchronized with the same clock signal (which is provided by the master device
bs via the SCK pin).
O To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 52) but master and
slave must be programmed with the same timing mode.
Doc ID 13841 Rev 1
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