UPSD3212B-40U6F(2009) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

UPSD3212B-40U6F
(Rev.:2009)

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

UPSD3212A, UPSD3212C, UPSD3212CV

22 PLDs

PLDs

PLDs bring programmable logic functionality to the UPSD. After specifying the logic for the

PLDs using PSDsoft Express, the logic is programmed into the device and available upon

Power-up.

Table 87. DPLD and CPLD Inputs

Input Source

Input Name

Number of

Signals

MCU Address Bus

A15-A0

16

MCU Control Signals

PSEN, RD, WR, ALE

4

RESET

RST

1

Power-down

PDN

1

Port A Input Macrocells(1)

PA7-PA0

8

Port B Input Macrocells

PB7-PB0

8

Port C Input Macrocells

PC2-4, PC7

4

Port D Inputs

PD2-PD1

2

Page Register

PGR7-PGR0

8

Macrocell AB Feedback

MCELLAB.FB7-FB0

8

Macrocell BC Feedback

MCELLBC.FB7-FB0

8

Flash memory Program Status bit

Ready/Busy

1

Note: 1. These inputs are not available in the 52-pin package.

The PSD module contains two PLDs: the Decode PLD (DPLD), and the Complex PLD

(CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in

Section 22.2: Decode PLD (DPLD), and Section 22.3: Complex PLD (CPLD). Figure 53

shows the configuration of the PLDs.

The DPLD performs address decoding for Select signals for PSD module components, such

as memory, registers, and I/O ports.

The CPLD can be used for logic functions, such as loadable counters and shift registers,

state machines, and encoding and decoding logic. These logic functions can be constructed

using the Output Macrocells (OMC), Input Macrocells (IMC), and the AND Array. The CPLD

can also be used to generate External Chip Select (ECS1-ECS2) signals.

The AND Array is used to form product terms. These product terms are specified using

PSDsoft. The PLD input signals consist of internal MCU signals and external inputs from the

I/O ports. The input signals are shown in Table 87.

22.1

Turbo bit in PSD module

The PLDs can minimize power consumption by switching off when inputs remain unchanged

for an extended time of about 70ns. Resetting the Turbo bit to '0' (Bit 3 of PMMR0)

automatically places the PLDs into standby if no inputs are changing. Turning the Turbo

mode off increases propagation delays while reducing power consumption.

119/181

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