UPSD3214B-40U6(2009) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

UPSD3214B-40U6
(Rev.:2009)

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

UPSD3212A, UPSD3212C, UPSD3212CV

Table 88. DPLD logic array

3

CSBOOT 0

3

CSBOOT 1

PLDs

22.3

I /O PORTS (PORT A,B,C)1

(INPUTS)

(20)

MCELLAB.FB [7:0] (FEEDBACKS) (8)

MCELLBC.FB [7:0] (FEEDBACKS) (8)

PGR0 -PGR7

(8)

A[15:0]2

(16)

PD[2:1]

(2)

PDN (APD OUTPUT)

(1)

PSEN, RD, WR, ALE2

(4)

RESET 2

(1)

RD_BSY

(1)

1. Port A inputs are not available in the 52-pin package

2. Inputs from the MCU module

3

FS0

3

FS1 4 PRIMARY FLASH

MEMORY SECTOR

3

FS2 SELECTS

3

FS3

2

RS0

SRAM SELECT

1

CSIOP

I/O DECODER

SELECT

1

PSEL0

PERIPHERAL I/O

1

PSEL1

MODE SELECT

AI07436

Complex PLD (CPLD)

The CPLD can be used to implement system logic functions, such as loadable counters and

shift registers, system mailboxes, handshaking protocols, state machines, and random logic.

The CPLD can also be used to generate External Chip Select (ECS1-ECS2), routed to Port

D.

Although External Chip Select (ECS1-ECS2) can be produced by any Output Macrocell

(OMC), these External Chip Select (ECS1-ECS2) on Port D do not consume any Output

Macrocells (OMC).

As shown in Figure 54, the CPLD has the following blocks:

● 20 Input Macrocells (IMC)

● 16 Output Macrocells (OMC)

● Macrocell Allocator

● Product Term Allocator

● AND Array capable of generating up to 137 product terms

● Four I/O Ports.

Each of the blocks are described in the sections that follow.

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