UPSD3214B-24T1(2009) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

UPSD3214B-24T1
(Rev.:2009)

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

UPSD3212A, UPSD3212C, UPSD3212CV

I/O ports (PSD module)

23.10

Ports A and B – functionality and structure

Ports A and B have similar functionality and structure, as shown in Figure 59. The two ports

can be configured to perform one or more of the following functions:

● MCU I/O mode

● CPLD Output – Macrocells McellAB7-McellAB0 can be connected to Port A or Port B.

McellBC7-McellBC0 can be connected to Port B or Port C.

● CPLD Input – Via the Input Macrocells (IMC).

● Latched Address output – Provide latched address output as per Table 92.

● Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew

rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain mode.

● Peripheral mode – Port A only (80-pin package)

Figure 59. Port A and Port B structure

WR

ADDRESS

ALE

DATA OUT

REG.

DQ

DQ

G

MACROCELL OUTPUTS

READ MUX

P

D

B

CONTROL REG.

DQ

WR

DIR REG.

DQ

WR

ENABLE PRODUCT TERM (.OE)

CPLD- INPUT

DATA OUT

ADDRESS

A[ 7:0]

OUTPUT

MUX

DATA IN

OUTPUT

SELECT

ENABLE OUT

PORT

A OR B PIN

INPUT

MACROCELL

AI06605

23.11

Port C – functionality and structure

Port C can be configured to perform one or more of the following functions (see Figure 60):

● MCU I/O mode

● CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or Port C.

● CPLD Input – via the Input Macrocells (IMC)

● In-System Programming (ISP) – JTAG pins (TMS, TCK, TDI, TDO) are dedicated pins

for device programming. (See Section 26: Programming in-circuit using the JTAG serial

interface, for more information on JTAG programming.)

● Open Drain – Port C pins can be configured in Open Drain mode

Port C does not support Address Out mode, and therefore no Control Register is required.

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