UPSD3213AV-24U1(2009) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

UPSD3213AV-24U1
(Rev.:2009)

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

Power management

UPSD3212A, UPSD3212C, UPSD3212CV

24.2

PSD chip select input (CSI, PD2)

PD2 of Port D can be configured in PSDsoft Express as PSD Chip Select Input (CSI). When

Low, the signal selects and enables the PSD module Flash memory, SRAM, and I/O blocks

for READ or WRITE operations. A High on PSD Chip Select Input (CSI, PD2) disables the

Flash memory, and SRAM, and reduces power consumption. However, the PLD and I/O

signals remain operational when PSD Chip Select Input (CSI, PD2) is High.

24.3

Input clock

CLKIN (PD1) can be turned off, to the PLD to save AC power consumption. CLKIN (PD1) is

an input to the PLD AND Array and the Output Macrocells (OMC).

During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic

equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from

the PLD AND Array or the Macrocells block by setting Bits 4 or 5 to a '1' in PMMR0.

24.4

Input control signals

The PSD module provides the option to turn off the MCU signals (WR, RD, PSEN, and

Address Strobe (ALE)) to the PLD to save AC power consumption. These control signals

are inputs to the PLD AND Array. During Power-down mode, or, if any of them are not being

used as part of the PLD logic equation, these control signals should be disabled to save AC

power. They are disconnected from the PLD AND Array by setting Bits 2, 3, 4, 5, and 6 to a

'1' in PMMR2.

Table 100. Power management mode registers (PMMR0)

Bit 0 X

0

Not used, and should be set to zero.

0 = off

Bit 1 APD Enable

1 = on

Automatic Power-down (APD) is disabled.

Automatic Power-down (APD) is enabled.

Bit 2 X

0

Not used, and should be set to zero.

0 = on PLD Turbo mode is on

Bit 3 PLD Turbo

1 = off

PLD Turbo mode is off, saving power.

UPSD321xx devices operate at 5MHz below the maximum rated

clock frequency

Bit 4

PLD Array

clk

0 = on

1 = off

CLKIN (PD1) input to the PLD AND Array is connected. Every

change of CLKIN (PD1) Powers-up the PLD when Turbo Bit is '0.'

CLKIN (PD1) input to PLD AND Array is disconnected, saving

power.

Bit 5

PLD MCell

clk

0 = on

1 = off

CLKIN (PD1) input to the PLD macrocells is connected.

CLKIN (PD1) input to PLD macrocells is disconnected, saving

power.

Bit 6 X

0

Not used, and should be set to zero.

Bit 7 X

0

Not used, and should be set to zero.

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