UPSD3212B-40T6F(2009) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

UPSD3212B-40T6F
(Rev.:2009)

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

RESET timing and device status at reset

UPSD3212A, UPSD3212C, UPSD3212CV

25 RESET timing and device status at reset

25.1

Upon Power-up, the PSD module requires a Reset (RESET) pulse of duration tNLNH-PO after

VCC is steady. During this period, the device loads internal configurations, clears some of

the registers and sets the Flash memory into operating mode. After the rising edge of Reset

(RESET), the PSD module remains in the Reset mode for an additional period, tOPR, before

the first memory access is allowed.

The Flash memory is reset to the READ mode upon Power-up. Sector Select (FS0-FS3 and

CSBOOT0-CSBOOT1) must all be Low, WRITE Strobe (WR, CNTL0) High, during Power-

on RESET for maximum security of the data contents and to remove the possibility of a byte

being written on the first edge of WRITE Strobe (WR). Any Flash memory WRITE cycle

initiation is prevented automatically when VCC is below VLKO.

Warm RESET

Once the device is up and running, the PSD module can be reset with a pulse of a much

shorter duration, tNLNH. The same tOPR period is needed before the device is operational

after a Warm RESET. Figure 65 shows the timing of the Power-up and Warm RESET.

25.2

I/O pin, register and PLD status at RESET

Table 103 shows the I/O pin, register and PLD status during Power-on RESET, Warm

RESET, and Power-down mode. PLD outputs are always valid during Warm RESET, and

they are valid in Power-on RESET once the internal Configuration bits are loaded. This

loading is completed typically long before the VCC ramps up to operating level. Once the

PLD is active, the state of the outputs are determined by the PLD equations.

Figure 65. Reset (RESET) timing

VCC

RESET

VCC(min)

tNLNH-PO

Power-On Reset

tOPR

tNLNH

tNLNH-A

Warm Reset

tOPR

AI02866b

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