UPSD3212A, UPSD3212C, UPSD3212CV
DC and AC parameters
Table 121. External data memory AC characteristics (with the 5 V MCU module)
Symbol
Parameter(1)
40 MHz oscillator
Min.
Max.
Variable oscillator
1/tCLCL = 24 to 40 MHz
Min.
Max.
Unit
tRLRH RD pulse width
120
6 tCLCL – 30
ns
tWLWH WR pulse width
120
6 tCLCL – 30
ns
tLLAX2 Address hold after ALE
10
tCLCL – 15
ns
tRHDX RD to valid data in
75
5 tCLCL – 50 ns
tRHDX Data hold after RD
0
0
ns
tRHDZ Data float after RD
38
2 tCLCL – 12 ns
tLLDV ALE to valid data in
150
8 tCLCL – 50 ns
tAVDV Address to valid data in
150
9 tCLCL – 75 ns
tLLWL ALE to WR or RD
60
90
3 tCLCL – 15 tCLCL + 15 ns
tAVWL Address valid to WR or RD
70
4 tCLCL – 30
ns
tWHLH WR or RD High to ALE High
10
40
tCLCL – 15 tCLCL + 15 ns
tQVWX Data valid to WR transition
5
tCLCL – 20
ns
tQVWH Data set-up before WR
125
7 tCLCL – 50
ns
tWHQX Data hold after WR
5
tCLCL – 20
ns
tRLAZ Address float after RD
0
0
ns
1. Conditions (in addition to those in Table 110, VCC = 4.5 to 5.5 V): VSS = 0 V; CL for Port 0, ALE and PSEN
output is 100 pF; CL for other outputs is 80 pF
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